US 12,321,308 B2 · Integrated circuit (IC) devices with efficient pin-sharing for multiprotocol communication interface

Abstract

Systems and methods related to communication interface are provided. An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement including serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port; inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the I2C data port and the SPI data port are electrically coupled to a second connection port; pattern detection circuitry to detect a signal pattern at a third connection port, the third connection port electrically coupled to the SPI CS port; and selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.

Claims20

Dependent claims

An interface circuitry arrangement for communication between integrated circuit (IC) devices, the interface circuitry arrangement comprising:

serial peripheral interface (SPI) circuitry having an SPI clock port, an SPI data port, and an SPI chip select (CS) port;
inter-integrated circuit (I2C) circuitry having an I2C clock port and an I2C data port, wherein the I2C clock port and the SPI clock port are electrically coupled to a first connection port, and wherein the 12C data port and the SPI data port are electrically coupled to a second connection port;
pattern detection circuitry to detect a signal pattern at a third connection port, the pattern detection circuitry comprising a counter to count edges of a CS signal received at the third connection port, the signal pattern comprising a plurality of edges of the CS signal, the third connection port electrically coupled to the SPI CS port, and the third connection port configured to (a) operate as an I2C address terminal for a bit of an I2C address when the I2C circuitry is active and (b) provide the CS signal to the SPI CS port when the SPI circuitry is active;
and
selection circuitry to selectively couple the SPI circuitry or the I2C circuitry to a data path responsive to an output of the pattern detection circuitry.

2 more elements

An integrated circuit (IC) device comprising:

a register memory;
an interface circuitry coupled to the register memory, the interface circuitry comprising:
a serial peripheral interface (SPI);
and
an inter-integrated circuit (I2C) interface;
a first terminal coupled to a chip select (CS) line of the SPI, wherein the first terminal operates as an I2C address terminal for a bit of an I2C address when the I2C interface is active, and wherein the first terminal operates as a CS terminal for the SPI when the SPI is active;
a second terminal coupled to a first data line of the SPI;
a third terminal coupled to a clock line of the SPI and a clock line of the I2C interface;
a fourth terminal coupled to a second data line of the SPI and a data line of the I2C interface;
mode detection circuitry coupled to the first terminal, wherein the mode detection circuitry;
comprises a counter to count negative edges of a signal on the CS line of the SPI,
monitors for a pattern comprising a plurality of negative edges of the signal on the CS line of the SPI, and
generates a selection signal for selecting the SPI or the I2C interface based on monitoring for the pattern;
and
selection circuitry to selectively couple the SPI or the I2C interface to the register memory based on the selection signal.

12 more elements

Dependencies are inferred from the claim text.

Integrated circuit (IC) devices with efficient pin-sharing for multiprotocol communication interface

Life of this patent

Integrated circuit (IC) devices with efficient pin-sharing for multiprotocol communication interface

Life of this patent

Abstract

Claims20