Multiple and cascaded redundant disciplined oscillator systems in a spoofing resistant reference time source system and methods thereof

A non-transitory computer readable medium having stored thereon instructions comprising executable code which when executed by at least one processor, cause the processor to:

• enter three or more redundant oscillators and a cascaded oscillator of a spoofing resistant reference time source system into an initialization state:
• discipline all but one of the redundant oscillators to a time and frequency external input into normal disciplining steady state with the remaining one of the redundant oscillators in a holdover state;
• when the all but one of the redundant oscillators have reached the normal disciplining steady state, place the all but one of the redundant oscillators into the holdover state, discipline the remaining one of the redundant oscillators to the time and frequency external input, and discipline the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state;
• and
• when the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining steady state, transition from an initialization stage to a steady state management stage.

A method comprising:

• entering, by a computing device, three or more redundant oscillators and a cascaded oscillator of a spoofing resistant reference time source system into an initialization state:
• disciplining, by the computing device, all but one of the redundant oscillators to a time and frequency external input into normal disciplining steady state with the remaining one of the redundant oscillators in a holdover state;
• when all but one of the redundant oscillators have reached the normal disciplining steady state, placing, by the computing device, the all but one of the redundant oscillators into the holdover state, disciplining the remaining one of the redundant oscillators to the time and frequency external input, and disciplining the cascaded oscillator to one of the all but one of the redundant oscillators now in the holdover state;
• and
• when the remaining one of the redundant oscillators and the cascaded oscillator have reached the normal disciplining steady state, transitioning, by the computing device, from an initialization stage to a steady state management stage.