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US 12,317,519 B2Granted
Contaminant collection on SOI
AssigneeTexas Instruments Incorporated
InventorsHonglin Guo, Zachary K Lee, Jingjing Chen
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes an SOI substrate having a semiconductor layer over a buried insulator layer; the semiconductor layer contains white space regions that include a PWELL region. An electronic device includes an NWELL region in the semiconductor layer, a dielectric over the NWELL region, and a polysilicon plate over the dielectric. A sacrificial NWELL ring is adjacent to and separated from the NWELL region by a first gap.
Claims24
A semiconductor device, comprising:
- a semiconductor-on-insulator (SOI) substrate including a semiconductor layer on an insulator layer;
- an N-type well (NWELL) region in the semiconductor layer, the NWELL region including a semiconductor component;
- and
- a white space region in the semiconductor layer, the white space region laterally surrounding the NWELL region, wherein the white space region has a greater surface roughness than the NWELL region.
1 more element
A semiconductor device, comprising:
- a semiconductor-on-insulator (SOI) substrate including a semiconductor layer on an insulator layer;
- an N-type well (NWELL) region in the semiconductor layer, the NWELL region extended from a surface of the semiconductor layer;
- and
- a P-type well (PWELL) region in the semiconductor layer, the PWELL region laterally surrounding the NWELL region and extended from the surface of the semiconductor layer, wherein the PWELL region has a sheet resistance less than the NWELL region.
1 more element
Dependencies are inferred from the claim text.