Semiconductor device comprising work function metal pattern in boundary region and method for fabricating the same

A semiconductor device comprising:

• a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
• a boundary element isolation layer on the boundary region of the substrate;
• a high-k dielectric layer on the boundary region and the core region of the substrate;
• a first conductive pattern on the high-k dielectric layer and including a first extension portion on the boundary region of the substrate;
• a second conductive pattern on the first conductive pattern and including a second extension portion on the boundary region of the substrate;
• a third conductive pattern on the second conductive pattern and including a third extension portion on the boundary region of the substrate;
• and
• a bit line on the cell region,
• wherein a top surface of the boundary element isolation layer is exposed between the third extension portion of the third conductive pattern and the bit line,
• the top surface of the boundary element isolation layer includes a recess,
• a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern,
• the high-k dielectric layer includes a fourth extension portion on the boundary region,
• a length of the fourth extension portion of the high-k dielectric layer is greater than the length of the first extension portion of the first conductive pattern, and
• the third extension portion of the third conductive pattern directly contacts the boundary element isolation layer.

A semiconductor device comprising:

• a substrate including a cell region, a core region, and a boundary region between the cell region and the core region;
• a boundary element isolation layer on the boundary region of the substrate;
• a high-k dielectric layer on the boundary region and the core region of the substrate;
• and
• a gate structure including a first conductive pattern, a second conductive pattern, and a third conductive pattern, the first conductive pattern on the high-k dielectric layer and including a first extension portion on the boundary region of the substrate, the second conductive pattern on and directly in contact with the first conductive pattern and including a second extension portion on the boundary region of the substrate, the third conductive pattern on and directly in contact with the second conductive pattern and including a third extension portion on the boundary region of the substrate,
• wherein the high-k dielectric layer includes a fourth extension portion on the boundary region,
• a length of the second extension portion of the second conductive pattern is greater than a length of the first extension portion of the first conductive pattern, and is less than a length of the third extension portion of the third conductive pattern,
• the length of the second extension portion of the second conductive pattern is substantially same as the length of the fourth extension portion of the high-k dielectric layer, and
• the third extension portion of the third conductive pattern directly contacts the boundary element isolation layer.