# US 12,316,728 B2 · Phase and frequency error processing

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,316,728 B2
- Document ID: US12316728B2
- Status: Granted
- Kind: B2
- Application number: 17/659,803
- Filed: 2022-04-19
- Published: 2022-10-20
- Granted: 2025-05-27
- Earliest claimed: 2021-04-19
- Assignees: Microsemi Semiconductor ULC
- Applicants: Microsemi Semiconductor ULC
- Inventors: Xihao Li; Tariq Haddad
- Web page: https://patentgrep.com/patent/US12316728B2

## CPC

- H04J 3/0658: {Clock or time synchronisation among packet nodes}
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H03L 7/0805: {the loop being adapted to provide an additional control signal for use outside the loop}
- H03L 7/0807: {concerning mainly a recovery circuit for the reference signal}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H04L 7/0033: {Correction by delay}
- H04J 3/0667: {Bidirectional timestamps, e.g. NTP or PTP for compensation of clock drift and for compensation of propagation delays (arrangements for monitoring round trip delays in packet switching networks H04L43/0864)}
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

One or more examples relate, generally to phase and frequency error processing. An apparatus includes a phase path and a frequency path. The phase path processes phase error of communications between network nodes. The phase path includes a closed-loop feedback loop controller. The frequency path processes frequency error of the communications between the network nodes. The frequency path is separate from the phase path. A method of processing phase error and frequency error includes selecting first packets for phase processing, processing the first packets for phase error, selecting second packets for frequency processing, and processing the second packets for frequency error independently of the processing of the first packets.

## Claims

### Claim 1

An apparatus, comprising:
a phase path to process phase error of communications between network nodes, the phase path including a closed-loop feedback loop controller; and
a frequency path to process frequency error of the communications between the network nodes, the frequency path separate from the phase path,
wherein a phase bandwidth of the apparatus is independent from a frequency bandwidth of the apparatus.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the phase bandwidth and the frequency bandwidth are programmable.

### Claim 3 (depends on 1)

The apparatus of claim 1, wherein the phase path includes a phase slope limiter.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the frequency path includes a frequency change limiter.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the frequency path includes an open-loop frequency estimator.

### Claim 6 (depends on 5)

The apparatus of claim 5, wherein the open-loop frequency estimator is implemented as an open-loop low-pass filter to enable multipath monitoring.

### Claim 7

An apparatus, comprising:
a phase path to process phase error of communications between network nodes, the phase path including a closed-loop feedback loop controller; and
a frequency path to process frequency error of the communications between the network nodes, the frequency path separate from the phase path,
wherein the frequency path is to processes one of a forward packet stream, a reverse packet stream, or combined phase data from the forward packet stream and the reverse packet stream.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the one of the forward packet stream, the reverse packet stream, or the combined phase data is selectable to be processed by the frequency path responsive to noise levels of the forward packet stream and the reverse packet stream.

### Claim 9

An apparatus, comprising:
a phase path to process phase error of communications between network nodes, the phase path including a closed-loop feedback loop controller; and
a frequency path to process frequency error of the communications between the network nodes, the frequency path separate from the phase path,
wherein the closed-loop feedback loop controller includes a closed-loop phase locked loop (PLL) controller,
wherein the closed-loop PLL controller is free of an integral portion.

### Claim 10

An apparatus, comprising:
a phase path to process phase error of communications between network nodes, the phase path including a closed-loop feedback loop controller; and
a frequency path to process frequency error of the communications between the network nodes, the frequency path separate from the phase path,
wherein a total bandwidth of the phase path in parallel with the frequency path is a greater one of a phase bandwidth of the phase path and a frequency bandwidth of the frequency path.

### Claim 11

An apparatus, comprising:
a phase path to process phase error of communications between network nodes, the phase path including a closed-loop feedback loop controller; and
a frequency path to process frequency error of the communications between the network nodes, the frequency path separate from the phase path,
wherein a total damping factor of the phase path in parallel with the frequency path is a ratio of a phase bandwidth of the phase path to a frequency bandwidth of the frequency path.

### Claim 12

A method of processing phase error and frequency error, the method comprising: selecting first packets for phase processing;
processing the first packets for the phase error;
selecting second packets for frequency processing; and
processing the second packets for the frequency error independently of the processing of the first packets,
wherein selecting first packets for phase processing comprises compensating phase values of the first packets with a previous phase adjustment and a previous frequency adjustment.

### Claim 13 (depends on 12)

The method of claim 12, wherein processing the second packets includes filtering the second packets utilizing an open-loop low-pass filter.

### Claim 14

A method of processing phase error and frequency error, the method comprising:
selecting first packets for phase processing;
processing the first packets for the phase error;
selecting second packets for frequency processing; and
processing the second packets for the frequency error independently of the processing of the first packets, wherein selecting second packets for frequency processing comprises compensating phase values of the second packets with a previous phase adjustment and a previous frequency adjustment.

### Claim 15

A method of processing phase error and frequency error, the method comprising:
selecting first packets for phase processing;
processing the first packets for the phase error;
selecting second packets for frequency processing; and
processing the second packets for the frequency error independently of the processing of the first packets,
wherein selecting the first packets for the phase processing comprises selecting the first packets responsive to a minimum transit time.

### Claim 16

A method of processing phase error and frequency error, the method comprising:
selecting first packets for phase processing;
processing the first packets for the phase error;
selecting second packets for frequency processing; and
processing the second packets for the frequency error independently of the processing of the first packets,
wherein selecting the second packets for the frequency processing comprises selecting the second packets responsive to one of a minimum transit time or a mean transit time.

### Claim 17

An apparatus comprising:
a network interface terminal of a network node, the network interface terminal to deliver and receive communication packets to and from one or more other network nodes; and
processing circuitry to:
process, by a closed-loop phase locked loop (PLL) controller, phase error of the communication packets communicated between the network node and the one or more other network nodes; and
process frequency error of the communication packets communicated between the network node and the one or more other network nodes independently from the closed-loop PLL controller,
wherein a phase bandwidth of the apparatus is independent from a frequency bandwidth of the apparatus.

### Claim 18 (depends on 17)

The apparatus of claim 17, wherein the processing circuitry is to process the frequency error using an open-loop frequency estimator.