Iterative decoding technique for correcting DRAM device failures

An error correction code (ECC) decoder configured to receive data from a memory, comprising:

• a syndrome generator configured to receive a codeword from the memory;
• an error-location polynomial generator coupled to an output of the syndrome generator;
• an error value generator;
• and
• an error location generator;
• wherein the error value generator and the error location generator are electrically coupled to an output of the error-location polynomial generator;
• wherein the error value generator and the error location generator (i) facilitate performing a single decoding attempt to detect random error symbols in a first portion of a word received from one memory component of a plurality of memory components of the memory and (ii) correct the detected random error;
• and
• wherein when the correcting of the detected random errors fails, iteratively performing decoding attempts with each attempt marking symbols in the remaining portions of the received word that correspond respectively to remaining memory components of the plurality of memory components, as erasures, and using counter logic to obtain erasure location information corresponding to the erasures.