Error processing and correction of adjacent 2-bit errors

A method, comprising:

• storing a sequence of bits in successive memory cells of a memory circuit;
• and
• using a processor circuit, which is coupled to the memory circuit, to carry out the following acts:
• processing errors in the sequence of bits, wherein the sequence of bits, in an error-free case, forms a codeword of an error code, wherein the error code is based on an H-matrix or is able to be determined by the H-matrix;
• determining an error syndrome for the sequence of bits;
• when the error syndrome is other than 0, determining a link between components of the error syndrome and parts of the H-matrix;
• inverting the components of the error syndrome when the corresponding linked components of columns of the H-matrix have an odd number of ones, and leaving the components of the error syndrome non-inverted when corresponding linked components of the columns of the H-matrix have an even number of ones;
• and
• determining a correction signal has a value of one or zero, where the correction signal has the value of one when the linked value of the error syndrome with the components of two adjacent columns has a predefined Boolean value, and wherein the correction signal has the value of zero when the linked value of the error syndrome with the components of two adjacent columns has a value other than the predefined Boolean value;
• and
• correcting two adjacent bits in the sequence of bits when the correction signal adopts the value of one.