US 12,315,584 B2 · Method for finding common optimal reference voltage and memory storage system

Abstract

This application relates to the technical field of data storage, and discloses a method for finding a common optimal reference voltage and a memory storage-system. The method includes: providing a lookup table for optimal reference voltage offset of each programmed state of target memory and a 1-bit count difference voltage offset corresponding to predetermined 1-bit count index at different time intervals; when there is a NAND device of a memory storage system with UECC or bit error rate exceeding criteria, detecting current 1-bit count difference voltage offset corresponding to the predetermined 1-bit count index, and obtaining optimal reference voltage offset in the lookup table with the current 1-bit count difference voltage offset as index; and applying the corresponding reference voltage offset to initial common reference voltage of all NAND devices of the memory storage system. This application can accurately adjust the reference voltage.

Claims13

Dependent claims

A method for finding a common optimal reference voltage, comprising:

providing a lookup table for a reference voltage offset corresponding to each read reference voltage between two adjacent states and a 1-bit count difference voltage offset corresponding to predetermined 1-bit count index at different time intervals;
when there is a NAND device of a memory storage system with UECC or bit error rate exceeding criteria, detecting current 1-bit count difference voltage offset corresponding to the predetermined 1-bit count index, and obtaining a reference voltage offset corresponding to each read reference voltage between two adjacent states in the lookup table with the current 1-bit count difference voltage offset as index;
and
applying the corresponding reference voltage offset to initial common optimal read reference voltage of all NAND devices of the memory storage system.

1 more element

A memory storage system, comprising:

one or more NAND devices;
and
a memory controller coupled to the one or more NAND devices, the memory controller storing a lookup table for a reference voltage offset corresponding to each read reference voltage between two adjacent states and a 1-bit count difference voltage offset corresponding to predetermined 1-bit count index at different time intervals, wherein the memory controller is configured to:
when there is a NAND device of the memory storage system with UECC or bit error rate exceeding criteria, detect current 1-bit count difference voltage offset corresponding to the predetermined 1-bit count index, and obtain a reference voltage offset corresponding to each read reference voltage between two adjacent states in the lookup table with the current 1-bit count difference voltage offset as index, and apply the corresponding reference voltage offset to initial common reference voltage of all NAND devices of the memory storage system.

1 more element

Dependencies are inferred from the claim text.

Method for finding common optimal reference voltage and memory storage system

Life of this patent

Method for finding common optimal reference voltage and memory storage system

Life of this patent

Abstract

Claims13