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US 12,314,719 B2Granted
Multi-indexed micro-operations cache for a processor
AssigneeNokia Solutions and Networks Oy
InventorPranjal Kumar Dutta
Life of this patent
Estimating the term…
Abstract
Various example embodiments for supporting a multi-indexed micro-operations cache (MI-UC) in a processor are presented. Various example embodiments for supporting an MI-UC in a processor may be configured to support an MI-UC in which, for a UC line of the MI-UC, multiple indexes into the UC line, for multiple sets of micro-operations (UOPs) stored in the UC line based on decoding of multiple instructions, are supported.
Claims16
An apparatus, comprising:
- a decode unit configured to decode a plurality of instructions of a program to form a respective plurality of sets of micro-operations;
- and
- a micro-operations cache configured to:
- store, in a cache line of the micro-operations cache, the plurality of sets of micro-operations;
- and
- store, for the cache line of the micro-operations cache, a set of entries including:
- for a first instruction in the plurality of instructions of the program for which the respective set of micro-operations is stored at a beginning of the cache line of the micro-operations cache, a first entry including an identifier of the first instruction, wherein the identifier of the first instruction includes an instruction pointer tag for the first instruction and an instruction pointer offset for the first instruction;
- and
- for each instruction in the plurality of instructions of the program other than the first instruction, a respective entry including an identifier of the respective instruction and a micro-operation offset for the respective instruction, wherein the identifier of the respective instruction is an instruction pointer offset for the respective instruction and wherein the micro-operation offset for the respective instruction is indicative of a location of the respective set of micro-operations of the respective instruction in the cache line of the micro-operations cache.
6 more elements
An apparatus, comprising:
- a decode unit configured to decode a first instruction into a first set of micro-operations and a second instruction into a second set of micro-operations;
- and
- a micro-operations cache configured to:
- store, in a cache line of the micro-operations cache, the first set of micro-operations and the second set of micro-operations;
- store, for the cache line of the micro-operations cache, an identifier of the first instruction and an entry for the second instruction, wherein the entry for the second instruction includes an identifier of the second instruction and an indication of a location of the second set of micro-operations in the cache line of the micro-operations cache;
- compare the identifier of the second instruction with an identifier of a tag array entry of a tag array and compare an offset portion of the identifier of the second instruction against a set of intermediate entries of the tag array entry in parallel;
- and
- provide, from one of the intermediate entries of the tag array entry based on a determination that the offset portion of the identifier of the second instruction matches the one of the intermediate entries of the tag array entry, the indication of the location of the second set of micro-operations in the cache line of the micro-operations cache.
5 more elements
An apparatus, comprising:
- a decode unit configured to decode a plurality of instructions of a program to form a respective plurality of sets of micro-operations, wherein each of the instructions in the plurality of instructions of the program shares a common instruction pointer tag;
- and
- a micro-operations cache configured to:
- store, in a cache line of the micro-operations cache, the plurality of sets of micro-operations;
- and
- store, for the cache line of the micro-operations cache, a set of entries including, for each instruction in the plurality of instructions of the program, a respective entry configured to support retrieval of the respective set of micro-operations of the respective instruction from the cache line of the micro-operations cache based on the respective instruction, wherein the respective entry comprises a respective instruction offset configured for use in matching the respective instruction and a respective micro-operation offset indicative of a location of the respective set of micro-operations of the respective instruction in the cache line of the micro-operations cache.
3 more elements
Dependencies are inferred from the claim text.