Hybrid hardware accelerator and programmable array architecture

A system on a chip (SoC), comprising:

• an array of processing elements, each one of the processing elements being configured to perform processing operations on an array of data samples;
• a hardware accelerator;
• and
• a data interface comprising a buffer, the data interface being coupled to the array of processing elements and to the hardware accelerator,
• wherein the data interface is configured to transfer the array of data samples from the array of processing elements to the hardware accelerator by storing the array of data samples at an address location in the buffer based upon a respective one of the processing elements from which the array of data samples was received, and
• wherein the hardware accelerator is configured to compute, based upon the transferred array of data samples, a set of computed terms in accordance with a predetermined processing function to generate processed data samples including the set of computed terms.