Circuit layout for improving power supply rejection ratio
AssigneeRealtek Semiconductor Corp.
InventorsKuan-Yu Shih, Ying-Rong Su
Life of this patent
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AssigneeRealtek Semiconductor Corp.
InventorsKuan-Yu Shih, Ying-Rong Su
Estimating the term…
A circuit layout for improving the power supply rejection ratio includes a radio frequency (RF) choke and an inductor. The RF choke receives a supply voltage and includes: a first choke coil positioned in an ultra-thick metal (UTM) layer, the coil including a first choke electrode; and a second choke coil positioned in a redistribution layer (RDL), the coil including a second choke electrode. The inductor belongs to a main circuit and includes: a primary-side coil surrounding the first choke coil in the UTM layer, and being coupled to the first/second chock electrode and the main circuit's signal input circuit; and a secondary-side coil surrounding the first choke coil in the UTM layer and surrounding the second choke coil in the RDL, and being used for signal output. The inductor and the RF choke jointly form mutual induction to suppress the noise of the supply voltage.
A circuit layout for improving a power supply rejection ratio (PSRR), the circuit layout comprising:
A circuit layout for improving a power supply rejection ratio (PSRR), the circuit layout comprising:
A circuit layout for improving a power supply rejection ratio (PSRR), the circuit layout comprising:
Dependencies are inferred from the claim text.