Back to results
US 12,310,124 B2Granted
Photodiodes
AssigneeGlobalFoundries U.S. Inc.
InventorsRajendran Krishnasamy, John J. Ellis-Monaghan, Siva P. Adusumilli, Ramsey Hazbun, Steven M. Shank
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and methods of manufacture. The structure includes: a top terminal; an intrinsic material in contact with the top terminal; and a bottom terminal in contact with the intrinsic material, the bottom terminal including a P semiconductor material and a fully depleted N semiconductor material.
Claims18
A structure comprising:
- a top terminal comprising P+ semiconductor material;
- an intrinsic material touching the top terminal;
- a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material;
- and
- an isolation structure above the bottom terminal and an underlying semiconductor substrate, the isolation structure touching the intrinsic material.
2 more elements
A structure comprising:
- a top terminal comprising P+ semiconductor material;
- an intrinsic material touching the top terminal;
- a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material;
- a shallow trench isolation structure separating the intrinsic material from a drain region of the gate structure;
- and
- a gate structure pinned to the fully depleted N semiconductor material,
- wherein the bottom terminal is within a substrate material shared with the gate structure and the intrinsic material is within a trench in the substrate material.
4 more elements
A structure comprising:
- a pinned photodiode comprising a fully depleted semiconductor region, and an intrinsic region between an upper p-doped region and a lower n-doped region;
- a transistor pinned to the pinned photodiode;
- and
- an isolation structure touching the intrinsic semiconductor material and the lower n-doped region, both above the fully depleted semiconductor region, and separating a drain region of the transistor that is over the lower n-doped region from the intrinsic semiconductor material.
1 more element
A method comprising:
- forming a top terminal comprising P+ semiconductor material;
- forming an intrinsic material touching the top terminal;
- forming a bottom terminal in contact the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material;
- and
- forming an isolation structure above the bottom terminal and an underlying semiconductor substrate, the isolation structure touching the intrinsic material.
2 more elements
A structure comprising:
- a top terminal comprising P+ semiconductor material;
- an intrinsic material touching the top terminal;
- a bottom terminal in contact with the intrinsic material, the bottom terminal comprising a P semiconductor material and a fully depleted N semiconductor material;
- and
- an isolation structure above the bottom terminal, and adjacent to and touching the intrinsic material above and to a side of the bottom terminal, and wherein the bottom terminal touches the intrinsic material.
2 more elements
Dependencies are inferred from the claim text.