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US 12,310,079 B2Granted
Semiconductor devices including gate spacer
AssigneeSamsung Electronics Co., Ltd.
InventorsBongseok Suh, Daewon Kim, Beomjin Park, Sukhyung Park, Sungil Park, Jaehoon Shin, Bongseob Yang, Junggun You, Jaeyun Lee
Life of this patent
Estimating the term…
Abstract
A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.
Claims19
A semiconductor device, comprising:
- a first active region defined on a substrate and including a plurality of channel regions;
- a first gate electrode across the first active region and surrounding a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions;
- a first gate dielectric layer between the first active region and the first gate electrode;
- a first drain region in the first active region at a position adjacent to the first gate electrode and in contact with each of the plurality of channel regions;
- a first gate spacer on a side surface of the first gate electrode;
- a second active region defined in a second region on the substrate;
- a second gate electrode across the second active region and having a larger horizontal width than the first gate electrode;
- a second drain region in the second active region at a position adjacent to the second gate electrode;
- an undercut region between the second active region and a metal portion of the second gate electrode;
- and
- a second gate spacer on a side surface of the second gate electrode and protruding into the undercut region;
- and
- a lower gate dielectric layer between the second active region and the second gate electrode and having a smaller horizontal width than the second gate electrode.
10 more elements
A semiconductor device, comprising:
- a first active region defined in a first region on a substrate;
- a first gate electrode across the first active region;
- a first gate dielectric layer between the first active region and the first gate electrode;
- a first drain region in the first active region at a position adjacent to the first gate electrode;
- a first gate spacer on a side surface of the first gate electrode;
- a second active region defined in a second region on the substrate;
- a second gate electrode across the second active region and having a larger horizontal width than the first gate electrode;
- a second drain region in the second active region at a position adjacent to the second gate electrode;
- an undercut region between the second active region and a metal portion of the second gate electrode;
- a second gate spacer on a side surface of the second gate electrode and protruding into the undercut region;
- and
- a lower gate dielectric layer between the second active region and the second gate electrode,
- wherein a lower end of at least one of the first gate electrode and the second gate electrode is disposed lower than an upper end of one of the first active region corresponding to the first gate electrode and the second active region corresponding to the second gate electrode,
- wherein the first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, and
- wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions.
12 more elements
A semiconductor device, comprising:
- a first active region defined in a first region on a substrate;
- a first gate electrode across the first active region;
- a first drain region in the first active region at a position adjacent to the first gate electrode;
- a second active region defined in a second region on the substrate;
- a second gate electrode across the second active region;
- a second drain region in the second active region at a position adjacent to the second gate electrode;
- an undercut region between the second active region and a metal portion of the second gate electrode;
- a second gate spacer on a side surface of the second gate electrode and protruding into the undercut region;
- a lower gate dielectric layer between the second active region and the second gate electrode;
- and
- a second gate dielectric layer extending between the second gate electrode and the second gate spacer,
- wherein the second gate spacer has a shape of inverted T,
- wherein a lower end of the second gate electrode is disposed lower than an upper end of the second active region,
- wherein the first active region includes a plurality of channel regions, each of the plurality of channel regions being in contact with the first drain region, and
- wherein the first gate electrode surrounds a top surface, a side surface, and a bottom surface of at least one of the plurality of channel regions.
12 more elements
Dependencies are inferred from the claim text.