Back to results
US 12,310,046 B2Granted
Enhanced MOSFET with superior RF performance
AssigneeQUALCOMM Incorporated
InventorsAbhijeet Paul, Ravi Pramod Kumar Vedula, Hyunchul Jung
Life of this patent
Estimating the term…
Abstract
Disclosed is a transistor of a device that has an asymmetric resistance or an asymmetric capacitive coupling or both. When used in a cascode configuration in an amplifier, low current performance of the amplifier is improved. Asymmetric resistance may be enabled through differentially doping source and drain structures of the transistor and/or through differentially manipulating geometries the source and drain structures. Asymmetric capacitive coupling may be enabled through providing dielectrics and differentially locating the dielectrics above a gate of the transistor. Further, a body of the transistor may be biased.
Claims25
A transistor, comprising:
- a first dielectric layer on an implant layer;
- a source contact, a drain contact, and a gate structure within the first dielectric layer, the gate structure being between the source contact and the drain contact and comprising a gate oxide, a gate on the gate oxide, a source side spacer on sides of the gate and the gate oxide facing the source contact, and a drain side spacer on sides of the gate and the gate oxide facing the drain contact;
- a source implant structure within the implant layer and electrically coupled with the source contact, the source implant structure comprising a source well below the source contact, a source extension extending from the source well to below at least a portion of the source side spacer, and a source halo below the source extension and vertically overlapping at least a part of the source side spacer;
- a drain implant structure within the implant layer and electrically coupled with the drain contact, the drain implant structure comprising a drain well below the drain contact, a drain extension extending from the drain well to below at least a portion of the drain side spacer, and a drain halo below the drain extension and vertically overlapping at least a part of the drain side spacer,
- wherein the transistor has an asymmetric resistance or an asymmetric capacitive coupling or both, the asymmetric resistance being when a resistance of the drain implant structure is different from a resistance of the source implant structure, and the asymmetric capacitive coupling being when a capacitive coupling between the gate and the source contact is different from a capacitive coupling between the gate and the drain contact;
- and
- a second dielectric within the first dielectric layer above the gate, a dielectric constant of the second dielectric being different from a dielectric constant of the first dielectric layer.
4 more elements
A method of fabricating a transistor, the method comprising:
- forming a first dielectric layer on an implant layer,
- forming a source contact, a drain contact, and a gate structure within the first dielectric layer, the gate structure being between the source contact and the drain contact and comprising a gate oxide, a gate on the gate oxide, a source side spacer on sides of the gate and the gate oxide facing the source contact, and a drain side spacer on sides of the gate and the gate oxide facing the drain contact;
- forming a source implant structure within the implant layer and electrically coupled with the source contact, the source implant structure comprising a source well below the source contact, a source extension extending from the source well to below at least a portion of the source side spacer, and a source halo below the source extension and vertically overlapping at least a part of the source side spacer;
- forming a drain implant structure within the implant layer and electrically coupled with the drain contact, the drain implant structure comprising a drain well below the drain contact, a drain extension extending from the drain well to below at least a portion of the drain side spacer, and a drain halo below the drain extension and vertically overlapping at least a part of the drain side spacer,
- wherein the transistor has an asymmetric resistance or an asymmetric capacitive coupling or both, the asymmetric resistance being when a resistance of the drain implant structure is different from a resistance of the source implant structure, and the asymmetric capacitive coupling being when a capacitive coupling between the gate and the source contact is different from a capacitive coupling between the gate and the drain contact;
- and
- forming a second dielectric within the first dielectric layer above the gate, a dielectric constant of the second dielectric being different from a dielectric constant of the first dielectric layer.
4 more elements
An amplifier comprising:
- an amplifying transistor, a source of the amplifying transistor being configured to receive a low voltage, and a gate of the amplifying transistor being configured to receive an input voltage;
- and
- a cascode transistor, a source of the cascode transistor being configured to connect with a drain of the amplifying transistor, a gate of the cascode transistor being configured to receive a bias voltage, and a drain of the cascode transistor being configured to output an amplified version of the input voltage,
- wherein the cascode transistor has an asymmetric resistance or an asymmetric capacitive coupling or both, the asymmetric resistance of a transistor being when a resistance of a drain of the transistor is different from a resistance of a source of the transistor, and the asymmetric capacitive coupling of a transistor being when a capacitive coupling between a gate and a source of the transistor is different from a capacitive coupling between the gate and a drain of the transistor;
- wherein the cascode transistor comprises:
- a first dielectric layer on an implant layer;
- a source contact, a drain contact, and a gate structure within the first dielectric layer, the gate structure being between the source contact and the drain contact and comprising a gate oxide, the gate on the gate oxide, a source side spacer on sides of the gate and the gate oxide facing the source contact, and a drain side spacer on sides of the gate and the gate oxide facing the drain contact;
- a source implant structure within the implant layer and electrically coupled with the source contact, the source implant structure comprising a source well below the source contact, a source extension extending from the source well to below at least a portion of the source side spacer, and a source halo below the source extension and vertically overlapping at least a part of the source side spacer;
- and
- a drain implant structure within the implant layer and electrically coupled with the drain contact, the drain implant structure comprising a drain well below the drain contact, a drain extension extending from the drain well to below at least a portion of the drain side spacer, and a drain halo below the drain extension and vertically overlapping at least a part of the drain side spacer;
- wherein the cascode transistor further comprises a body implant structure within the implant layer and electrically coupled with the source contact, the body implant structure comprising a body well, a body extension, and a body halo,
- wherein the body well is below the source contact and extends towards a body tap, the body tap being a portion of the gate that extends towards the source contact, the source side spacer being on a side of the body tap, the body well vertically overlapping the source side spacer and at least a first part of the body tap,
- wherein the body extension extends from the body well to below the gate structure and vertically overlaps at least a second part of the body tap, and
- wherein the body halo is below the body extension and vertically overlapping at least a third part of the body tap.
11 more elements
Dependencies are inferred from the claim text.