Decoder, decoding method, memory controller, and memory system
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsHua Tan, Dili Wang, Xuqing Jia
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Abstract
According to one aspect of the present disclosure, a decoder is provided. The decoder may include a cache module. The cache module may be configured to cache soft data related to a codeword to be decoded. The decoder may include a flip-indication module. The flip-indication module may be configured to obtain the soft data from the cache module. The flip-indication module may be configured to, when performing hard-decision decoding on the codeword to be decoded, determine, at least in a first flip iteration and with assistance of the soft data, a number of parity checks not satisfied by bits in the codeword to be decoded.
Claims16
A decoder, comprising:
- a cache module configured to:
- cache soft data related to a codeword to be decoded;
- and
- a flip-indication module configured to:
- obtain the soft data from the cache module, the soft data being expressed as a soft data vector;
- and
- perform hard-decision decoding on the codeword to be decoded, wherein, to perform the hard-decision decode on the codeword to be decoded, the flip-indication module is configured to:
- determine an initial error bit indication vector corresponding to the codeword to be decoded;
- perform a sum operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;
- and
- determine, at least in a first flip iteration of one or more flip iterations and with assistance of the soft data, a number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector,
- wherein each element in the target error bit indication vector corresponds to the number of parity checks not satisfied by one bit.
A method of decoding, comprising:
- obtaining soft data corresponding to a codeword to be decoded, the soft data being expressed as a soft data vector;
- and
- performing hard-decision decoding on the codeword to be decoded by:
- determining an initial error bit indication vector corresponding to the codeword to be decoded;
- performing a sum operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;
- and
- determining, at least in a first flip iteration of one or more flip iterations and with assistance of the soft data, a number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector,
- wherein each element in the target error bit indication vector corresponds to the number of parity checks not satisfied by one bit.
A memory system, comprising:
- a memory device configured to store data;
- a memory controller coupled to the memory device, wherein the memory controller comprises:
- a processor configured to:
- read soft data corresponding to a codeword to be decoded from the memory device, the soft data being expressed as a soft data vector;
- and
- a decoder configured to:
- cache the soft data;
- and
- perform hard-decision decoding on the codeword to be decoded, wherein, to perform the hard-decision decode on the codeword to be decoded, the decoder is configured to:
- determine an initial error bit indication vector corresponding to the codeword to be decoded;
- perform a sum operation on the soft data vector and the initial error bit indication vector to obtain a target error bit indication vector;
- and
- determine, at least in a first flip iteration of one or more flip iterations and with assistance of the soft data, a number of parity checks not satisfied by each bit in the codeword to be decoded according to the target error bit indication vector,
- wherein each element in the target error bit indication vector corresponds to the number of parity checks not satisfied by one bit.
Dependencies are inferred from the claim text.