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US 12,308,801 B2Granted
Back-gate controlled power amplifier
AssigneeGlobalFoundries U.S. Inc.
InventorsYiching Chen, Zhixing Zhao
Life of this patent
Estimating the term…
Abstract
The present disclosure relates to semiconductor structures and, more particularly, to a differential circuit with automatic parasitic neutralization and gain boost and methods of manufacture. The structure includes a plurality of auxiliary circuit devices with back-gate controls to perform a boost gain, and a differential pair of circuit devices which are connected to the auxiliary circuit devices.
Claims20
A structure comprising:
- a plurality of auxiliary circuit devices comprising back-gate controls to perform a boost gain;
- and
- a differential pair of circuit devices connected to the plurality of auxiliary circuit devices,
- wherein a first transistor of the differential pair of circuit devices shares a gate with a first transistor of the plurality of auxiliary circuit devices and a second transistor of the differential pair of circuit devices shares a separate gate with a second transistor of the plurality of auxiliary circuit devices, and a drain of the first transistor of the differential pair of circuit devices is connected to a drain of the second transistor of the plurality of auxiliary circuit devices, and the differential pair of circuit devices and the plurality of auxiliary circuit devices are formed on a triple-well neighboring n-well layout, and the plurality of auxiliary circuit devices being formed over a shared well.
1 more element
A structure comprising:
- a first transistor of a plurality of auxiliary circuit devices comprising a back-gate connected to a divided current control and a source connected to a current source;
- a second transistor of the plurality of auxiliary circuit devices comprising a back-gate connected to the divided current control and a source connected to the current source;
- the divided current control controls a gain using the first-back gate of the first transistor and the second back-gate of the second transistor;
- and
- a differential pair of circuit devices comprising a first transistor having a gate shared with the first transistor of the plurality of auxiliary circuit devices, a second transistor of the differential pair of circuit devices sharing a separate gate with the second transistor of the plurality of auxiliary circuit devices, a drain of the first transistor of the differential pair of circuit devices being connected to a drain of the second transistor of the plurality of auxiliary circuit devices, and a drain of the second transistor of the differential pair of circuit devices being connected to a drain of the first transistor of the plurality of auxiliary circuit devices, and the differential pair of circuit devices and the plurality of auxiliary circuit devices are formed on a triple-well neighboring n-well layout, and the plurality of auxiliary circuit devices being formed over a shared well.
2 more elements
A structure comprising:
- a substrate comprising a plurality of p-wells in a back-gate region on a fully depleted semiconductor on insulator (FDSOI) substrate;
- a differential pair of main transistors over a plurality of n-wells;
- a plurality of auxiliary devices over the plurality of p-wells;
- and
- a continuous active region shared by the differential pair of transistors and the plurality of auxiliary devices,
- wherein a first transistor of the differential pair of main transistors shares a gate with the first transistor of the plurality of auxiliary devices and a second transistor of the differential pair of main transistors shares a separate gate with the second transistor of the plurality of auxiliary devices, and a drain of the first transistor of the differential pair of main transistors is connected to a drain of the second transistor of the plurality of auxiliary devices and a drain of the second transistor of the differential pair of main transistors is connected to a drain of the first transistor of the plurality of auxiliary devices, and the differential pair of circuit devices and the plurality of auxiliary devices are formed on a triple-well neighboring n-well layout, and the plurality of auxiliary devices being formed over a shared p-well.
3 more elements
Dependencies are inferred from the claim text.