Multi-chip package having stress relief structure

A method of manufacturing a semiconductor device, comprising:

• providing a package substrate;
• providing a first die group bonded onto the package substrate, the first die group characterized by a first thickness;
• bonding a second die group onto the package substrate, the second die group characterized by a second thickness;
• providing a carrier substrate on the first die group and characterized by a third thickness that is a function of a difference between the first thickness and the second thickness, wherein the carrier substrate comprises:
• a trench;
• a dielectric material in the trench;
• and
• an air gap encapsulated in the dielectric material;
• and
• providing a molding compound material on the package substrate and covering the first die group and the second die group.

A method of manufacturing a semiconductor package, comprising:

• providing a substrate;
• providing a first die group comprising a first set of one or more dies, wherein the first die group is characterized by a first thickness;
• bonding a lower surface of the first die group to the substrate;
• providing a second die group comprising a second set of one or more dies, wherein the second die group is characterized by a second thickness larger than the first thickness;
• bonding the second die group to the substrate;
• providing a carrier substrate encapsulating at least one air gap, wherein the carrier substrate is characterized by a third thickness equal to or greater than a difference between the second thickness and the first thickness;
• and
• bonding a lower surface of the carrier substrate to an upper surface of the first die group.