Decision feedback equalization in semiconductor devices

A memory device comprising:

• a memory interface circuit coupled to a data channel;
• a memory cell array;
• a data buffer circuit;
• and
• a control logic circuit coupled to the memory interface circuit, the memory cell array, and the data buffer circuit,
• wherein the data buffer circuit comprises:
• a converter circuit configured to receive an input signal from the memory interface circuit and convert the input signal to a digital signal;
• and
• a compensation circuit coupled to the converter circuit, the compensation circuit comprising:
• a sampling circuit configured to receive the digital signal and generate an output signal, the output signal comprising a stream of bits to be transmitted at a plurality of consecutive clock cycles;
• and
• one or more equalizing circuits coupled to the sampling circuit, each of the one or more equalizing circuits being configured to receive a bit of an output feedback signal at a corresponding one of the consecutive clock cycles and generate a corresponding equalization output,
• wherein the sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits, and
• wherein the sampling circuit comprises an N-type metal-oxide-semiconductor (NMOS) switch, the sampling circuit is configured to receive the digital signal at a gate terminal of the NMOS switch, the one or more equalizing circuits are coupled to a drain terminal of the NMOS switch, and one or more capacitors are coupled to the drain terminal of the NMOS switch.

A method for compensating for data distortion from channel loss, the method comprising:

• receiving an input signal from a data channel;
• converting the input signal to a digital signal;
• generating a sampling output signal, the sampling output signal comprising a stream of bits to be transmitted at a plurality of consecutive clock cycles;
• and
• providing, to each of one or more equalizing circuits, a bit of an output feedback signal at a corresponding one of the consecutive clock cycles,
• wherein the sampling output signal is generated based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits, and
• wherein each of the one or more equalizing circuits comprises:
• a first feedback switch configured to receive the bit of the output feedback signal, a second feedback switch configured to receive a logic opposite of the bit of the output feedback signal, and one or more weighting control switches configured to receive a weighting control signal.

An electronic circuit, comprising:

• a converter circuit configured to convert an input signal to a digital signal;
• and
• a compensation circuit coupled to the converter circuit, the compensation circuit comprising:
• a sampling circuit configured to receive the digital signal and generate an output signal, the output signal comprising a stream of bits to be transmitted at a plurality of consecutive clock cycles;
• and
• one or more equalizing circuits coupled to the sampling circuit, each of the one or more equalizing circuits being configured to receive a bit of an output feedback signal at a corresponding one of the consecutive clock cycles and generate a corresponding equalization output,
• wherein the sampling circuit is configured to generate the output signal based on the digital signal and a sum of one or more equalization outputs of the one or more equalizing circuits,
• wherein the compensation circuit is a first compensation circuit, and the sampling circuit is a first sampling circuit, and
• wherein the electronic circuit further comprises a second compensation circuit, and the second compensation circuit comprises a second sampling circuit configured to receive the digital signal and generate the output feedback signal at the plurality of consecutive clock cycles.