Neural network processing with chained instructions

A hardware node comprising:

• a global register;
• a pipeline configured to process instructions, the pipeline including a matrix vector unit comprising at least one accumulator register, a first multifunction unit, wherein the first multifunction unit is connected to receive an input from the matrix vector unit, and a second multifunction unit, wherein the second multifunction unit is connected to receive an output from the first multifunction unit;
• and
• wherein the hardware node is further configured to:
• receive a first type of instruction from an input queue via the global register, wherein the first type of instruction can only be performed by the matrix vector unit, and perform the first type of instruction by the matrix vector unit and store a first result of the first type of instruction in the at least one accumulator register,
• receive a second type of instruction from the input queue via the global register, wherein the second type of instruction can only be performed by at least one of the first multifunction unit or the second multifunction unit, and perform the second type of instruction using the first multifunction unit, wherein performing comprises performing an operation on at least the first result of the first type of instruction, and generate a second result, and
• without storing the first result or the second result in the global register, pass the second result to the second multifunction unit.

A hardware node comprising:

• a global register;
• a pipeline configured to process instructions, the pipeline including a matrix vector unit comprising at least one accumulator register, a first multifunction unit, wherein the first multifunction unit is connected to receive an input from the matrix vector unit, and a second multifunction unit, wherein the second multifunction unit is connected to receive an output from the first multifunction unit, and wherein each of the first multifunction unit and the second multifunction unit comprises at least one of a pointwise addition or a no-operation block;
• and
• wherein the hardware node is further configured to:
• receive a first type of instruction from an input queue via the global register, wherein the first type of instruction can only be performed by the matrix vector unit, and perform the first type of instruction by the matrix vector unit and store a first result of the first type of instruction in the at least one accumulator register,
• receive a second type of instruction from the input queue via the global register, wherein the second type of instruction can only be performed by at least one of the first multifunction unit or the second multifunction unit, and perform the second type of instruction using the first multifunction unit, wherein performing comprises performing an operation on at least the first result of the first type of instruction, and generate a second result, and
• without storing the first result or the second result in the global register, pass the second result to the second multifunction unit.