Compute in memory three-dimensional non-volatile nor memory for neural networks

A method, comprising:

• receiving an input vector including a first plurality of multi-bit activations for a first layer of a neural network;
• and
• performing a compute in memory multiplication between the input vector for the first layer of the neural network and a plurality of multi-bit weight values of the first layer of the neural network, a first plurality of the plurality of the multi-bit weight values stored encoded in a corresponding first plurality of memory cells as threshold voltages, the first plurality of memory cells connected in parallel between a first bit line and a first source line, the compute in memory multiplication is performed by:
• converting the first plurality of multi-bit activations for the first layer of the neural network into a corresponding first plurality of input voltage levels, each of the first plurality of input voltage levels being less than the threshold voltages of the first plurality of memory cells storing the multi-bit weight values to thereby operate the first plurality of memory cells in a subthreshold region;
• biasing the first bit line;
• while biasing the first bit line, concurrently applying each of the first plurality of input voltage levels to a corresponding one of the first plurality of memory cells;
• and
• determining a current on the first source line in response to concurrently applying the first plurality of input voltage levels to the corresponding ones of the first plurality of memory cells while biasing the first bit line.

A non-volatile memory device, comprising:

• an array of non-volatile memory cells each programmable to one of a plurality of threshold voltage values corresponding to a multi-bit state, the array having a three dimensional NOR architecture formed over a substrate and comprising a plurality of NOR strings, each of the NOR strings comprising a plurality of memory cells connected in parallel between a local bit line and a local source line running perpendicularly to a surface of the substrate, each of the memory cells connected to a corresponding word line running parallel to the substrate and having a channel that runs parallel to the substrate;
• one or more control circuits connected to the array of non-volatile memory cells and configured to:
• bias the local bit line of a first of the NOR stings;
• while biasing the local bit line of the first NOR string, concurrently applying one of a plurality of word line voltages to each of a plurality of the word lines connected to a corresponding plurality of memory cells of the first NOR string, each of the plurality of word line voltages corresponding to one of a plurality of multi-bit input values, each of the plurality of word line voltages having a value less than the plurality of threshold voltage values corresponding to a multi-bit state to thereby operate the memory cells in the subthreshold region;
• and
• determining a cumulative amount of current flowing between the local bit line of the first NOR string and the local source line of the first NOR string through the corresponding plurality of memory cells of the first NOR string in response to applying the plurality of subthreshold word line voltages to the plurality of word lines while biasing the local bit line of the first NOR string.