System and method for optimizing fault coverage based on optimized test point insertion determinations for logical circuits

A system for optimizing fault coverage for logical circuits, comprising:

• a processor;
• a display with a user interface to display an optimized simulated new circuit;
• and
• a non-transitory computer readable medium programmed with computer readable code that upon execution by the processor causes the processor to:
• receive a set of training circuit data, wherein the set of training circuit data includes at least one training circuit;
• analyze the training circuit data for each training circuit in the set training circuit data to generate a set of training data, wherein the generation of training data includes selecting at least one candidate test point for training circuit, performing fault simulation on each training circuit and associated at least one candidate test point for each candidate test point and associated training circuit, and generating structured training data for each training circuit and associated candidate test point, based on the training circuit data, candidate test point, and fault simulation associated with each training circuit and associated candidate test point combination;
• train a learning segment on the set of training data to learn to predict a change in fault coverage based on the set of training data;
• generate at least one fault coverage model based on the learning of the learning segment, wherein the at least one fault coverage model predicts the change in fault coverage for a circuit;
• select a plurality of candidate test points for a new circuit;
• apply the at least one fault coverage model to the selected plurality of candidate test points to determine change in fault coverage for the new circuit;
• stimulate test point insertion of an optimized test point, wherein the optimized test point is the candidate test point that meets a set of test point insertion rules based on results of the application of the at least one fault coverage model to the plurality of candidate test points;
• analyze the new circuit with the optimized test point to determine if a set of fault coverage optimization rules are achieved;
• repeat the selecting, applying, simulating test point insertion, and analyzing steps above until the set of fault coverage optimization rules are achieved;
• display the new circuit with the optimized test point after the fault coverage optimizations rules are achieved.

A non-transitory computer readable medium programmed with computer readable code that upon execution by a processor causes the processor to execute a method for optimizing fault coverage for circuits, comprising:

• receiving a set of training circuit data, wherein the set of training circuit data includes at least one training circuit;
• analyzing the training circuit data for each training circuit in the set training circuit data to generate a set of training data, wherein the generation of training data includes selecting at least one candidate test point for training circuit, performing fault simulation on each training circuit and associated at least one candidate test point for each candidate test point and associated training circuit, and generating structured training data for each training circuit and associated candidate test point, based on the training circuit data, candidate test point, and fault simulation associated with each training circuit and associated candidate test point combination;
• training a learning segment on the set of training data to learn to predict a change in fault coverage based on the set of training data;
• generating at least one fault coverage model based on the learning of the learning segment, wherein the at least one fault coverage model predicts the change in fault coverage for a circuit;
• selecting a plurality of candidate test points for a new circuit;
• applying the at least one fault coverage model to the selected plurality of candidate test points to determine change in fault coverage for the new circuit;
• stimulating test point insertion of an optimized test point, wherein the optimized test point is the candidate test point that meets a set of test point insertion rules based on results of the application of the at least one fault coverage model to the plurality of candidate test points;
• analyzing the new circuit with the optimized test point to determine if a set of fault coverage optimization rules are achieved;
• repeating the selecting, applying, simulating test point insertion, and analyzing steps above until the set of fault coverage optimization rules are achieved;
• displaying the new circuit with the optimized test point after the fault coverage optimizations rules are achieved.