Back to results
US 12,306,244 B2Granted
Test circuit in chip and circuit test method
AssigneeHuawei Technologies Co., Ltd.
InventorsYu Huang, Changming Cui, Junlin Huang, Haitao Fu
Life of this patent
Estimating the term…
Abstract
A test circuit transmits input data of a test vector to a data distribution circuit using an input of a test bus, and transmits the input data of the test vector to a scan input channel in a circuit under test using the data distribution circuit. After scan of the circuit under test is completed, output data of the test vector on a scan output channel in the circuit under test is transmitted to an output of the test bus using the data distribution circuit, to complete testing of the circuit under test. A dynamic correspondence between the data distribution circuit and the test bus may be configured based on a specific test solution, so that a test resource can be dynamically allocated.
Claims18
A test circuit, comprising:
- a plurality of test sub-circuits respectively corresponding to a plurality of circuits under test, wherein a jth test sub-circuit in the plurality of test sub-circuits comprises Nj data distribution circuits, and the Nj data distribution circuits are configured to connect a corresponding circuit under test to a test bus;
- and
- in the jth test sub-circuit, first input terminals of the Nj data distribution circuits are respectively connected to Nj inputs of the test bus, output terminals of CIj data distribution circuits in the Nj data distribution circuits are respectively connected to CIj scan input channels in the circuit under test corresponding to the test sub-circuit, second input terminals of COj data distribution circuits in the Nj data distribution circuits are respectively connected to COj scan output channels in the circuit under test corresponding to the test sub-circuit, and output terminals of the Nj data distribution circuits are further connected to Nj outputs of the test bus, wherein Nj=max (CIj, COj);
- and
- wherein the data distribution circuit comprises a first selector and a first register, a first input terminal of the first selector is configured to operate as the first input terminal of the data distribution circuit, a second input terminal of the first selector is configured to operate as the second input terminal of the data distribution circuit, an output terminal of the first selector is connected to an input terminal of the first register, and an output terminal of the first register is configured to operate as the output terminal of the data distribution circuit.
2 more elements
A circuit test method, wherein the method is applicable to a case in which a circuit under test is tested by using a test circuit, and the test circuit comprises:
- a plurality of test sub-circuits respectively corresponding to a plurality of circuits under test, wherein a jth test sub-circuit in the plurality of test sub-circuits comprises Nj data distribution circuits, and the Nj data distribution circuits are configured to connect a corresponding circuit under test to a test bus;
- and
- in the jth test sub-circuit, first input terminals of the Nj data distribution circuits are respectively connected to Nj inputs of the test bus, output terminals of CIj data distribution circuits in the Nj data distribution circuits are respectively connected to CIj scan input channels in the circuit under test corresponding to the test sub-circuit, second input terminals of COj data distribution circuits in the Nj data distribution circuits are respectively connected to COj scan output channels in the circuit under test corresponding to the test sub-circuit, and output terminals of the Nj data distribution circuits are further connected to Nj outputs of the test bus, wherein Nj=max (CIj, COj);
- and
- the method comprises:
- generating configuration information and a test vector that comprises text excitation data of the circuit under test, wherein
- configuring a test circuit based on the configuration information;
- transmitting the test vector to a test bus, and transmitting the test vector to a scan input channel in the circuit under test by using the test circuit;
- transmitting test result data of the circuit under test to an output of the test bus by using the circuit under test.
6 more elements
A test circuit design method, comprising:
- obtaining a quantity of scan input channels and a quantity of scan output channels in each circuit under test and a bus bit width of a test bus;
- and
- configuring, on the test bus based on the bus bit width of the test bus and the quantity of scan input channels and the quantity of scan output channels in each circuit under test, a data distribution circuit in a test sub-circuit corresponding to each circuit under test, to generate the test circuit, wherein the test circuit comprises:
- a plurality of test sub-circuits respectively corresponding to a plurality of circuits under test, wherein a jth test sub-circuit in the plurality of test sub-circuits comprises Nj data distribution circuits, and the Nj data distribution circuits are configured to connect a corresponding circuit under test to a test bus;
- and
- in the jth test sub-circuit, first input terminals of the Nj data distribution circuits are respectively connected to Nj inputs of the test bus, output terminals of CIj data distribution circuits in the Nj data distribution circuits are respectively connected to CIj scan input channels in the circuit under test corresponding to the test sub-circuit, second input terminals of COj data distribution circuits in the Nj data distribution circuits are respectively connected to COj scan output channels in the circuit under test corresponding to the test sub-circuit, and output terminals of the Nj data distribution circuits are further connected to Nj outputs of the test bus, wherein Nj=max (CIj, COj), and
- a quantity of data distribution circuits in the test sub-circuit corresponding to each circuit under test is determined based on the quantity of scan input channels and the quantity of scan output channels in each circuit under test;
- and
- wherein the Nj data distribution circuits each comprises a first selector and a first register, a first input terminal of the first selector is configured to operate as the first input terminal of the Nj data distribution circuit, a second input terminal of the first selector is configured to operate as the second input terminal of the Nj data distribution circuit, an output terminal of the first selector is connected to an input terminal of the first register, and an output terminal of the first register is configured to operate as the output terminal of the Nj data distribution circuit.
6 more elements
Dependencies are inferred from the claim text.