# US 12,301,697 B2 · Heterogeneous clock management solution

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,301,697 B2
- Document ID: US12301697B2
- Status: Granted
- Kind: B2
- Application number: 17/132,058
- Filed: 2020-12-23
- Published: 2021-04-15
- Granted: 2025-05-13
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Vikram Dadwal; James Coleman; Alexander Slota
- Web page: https://patentgrep.com/patent/US12301697B2

## CPC

- H04L 7/04: Speed or phase control by synchronisation signals {(H04L7/0075 takes precedence)}
- H04L 7/042: {Detectors therefor, e.g. correlators, state machines (digital correlators in general G06F17/15)}
- G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators}
- G06F 1/14: Time supervision arrangements, e.g. real time clock
- H04Q 11/04: for time-division multiplexing {(H04Q11/0001 takes precedence)}
- H04Q 2213/13213: Counting, timing circuits
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

Systems and techniques for an heterogeneous clock management solution for industrial systems are described herein. In an example, a system includes a clock management circuit adapted to receive core timing information from a core of an integrated circuit. The clock management circuit is further adapted to correlate the core timing information with a reference clock. The clock management circuit is further adapted to output frequency and time offset of the reference clock to the core timing information. The system includes an execution circuit adapted to schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset. The execution circuit is further adapted to issue a command to execute the transaction at the scheduled time.

## Claims

### Claim 1

A system for heterogeneous clock management, the system comprising:
a clock management circuit to:
receive core timing information from a core of an integrated circuit;
correlate the core timing information with a reference clock; and
output, to the core of the integrated circuit, a frequency and time offset of the reference clock to the core timing information, for scheduling transactions with the core of the integrated circuit at an internal timing of the core of the integrated circuit relative to the reference clock.

### Claim 2 (depends on 1)

The system of claim 1, wherein correlating the core timing information with the reference clock is within a synchronization precision value of the core.

### Claim 3 (depends on 1)

The system of claim 1, wherein the reference clock is internal to the integrated circuit.

### Claim 4 (depends on 1)

The system of claim 1, wherein a source for the reference clock is a network interface clock.

### Claim 5 (depends on 1)

The system of claim 1, the system further comprising:
an execution circuit to:
schedule a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset; and
issue a command to execute the transaction at the scheduled time.

### Claim 6 (depends on 1)

The system of claim 1, the system further comprising:
the clock management circuit to:
detect clocks internal to the integrated circuit; and
detect clocks external to the integrated circuit.

### Claim 7 (depends on 1)

The system of claim 1, wherein a user is prompted for a preferred reference clock as the reference clock from the clocks internal to the integrated circuit and the clocks external to the integrated circuit.

### Claim 8

At least one non-transitory machine-readable medium including instructions for heterogeneous clock management of an integrated circuit, the instructions when executed by the integrated circuit, cause the integrated circuit to perform operations comprising:
receiving core timing information from a core of the integrated circuit;
correlating the core timing information with a reference clock; and
outputting, to the core of the integrated circuit, a frequency and time offset of the reference clock to the core timing information, for scheduling transactions with the core of the integrated circuit at an internal timing of the core of the integrated circuit relative to the reference clock.

### Claim 9 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, wherein correlating the core timing information with the reference clock is within a synchronization precision value of the core.

### Claim 10 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, wherein the reference clock is internal to the integrated circuit.

### Claim 11 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, wherein a source for the reference clock is a network interface clock.

### Claim 12 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, the operations further comprising:
scheduling a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset; and
issuing a command to execute the transaction at the scheduled time.

### Claim 13 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, the operations further comprising:
detecting clocks internal to the integrated circuit; and
detecting clocks external to the integrated circuit.

### Claim 14 (depends on 8)

The at least one non-transitory machine-readable medium of claim 8, wherein a user is prompted for a preferred reference clock as the reference clock from the clocks internal to the integrated circuit and the clocks external to the integrated circuit.

### Claim 15

A method for heterogeneous clock management, comprising:
receiving core timing information from a core of an integrated circuit;
correlating the core timing information with a reference clock; and
outputting, to the core of the integrated circuit, a frequency and time offset of the reference clock to the core timing information, for scheduling transactions with the core of the integrated circuit at an internal timing of the core of the integrated circuit relative to the reference clock.

### Claim 16 (depends on 15)

The method of claim 15, wherein correlating the core timing information with the reference clock is within a synchronization precision value of the core.

### Claim 17 (depends on 15)

The method of claim 15, wherein the reference clock is internal to the integrated circuit.

### Claim 18 (depends on 15)

The method of claim 15, wherein a source for the reference clock is a network interface clock.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
scheduling a transaction from the core at a scheduled time relative to the reference clock using the frequency and time offset; and
issuing a command to execute the transaction at the scheduled time.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
detecting clocks internal to the integrated circuit; and
detecting clocks external to the integrated circuit.