Analog-to-digital converter circuit

An analog-to-digital converter circuit comprising:

• a first converter circuit configured to generate a first digital code by performing analog-to-digital conversion on a basis of an input voltage;
• a second converter circuit configured to generate a second digital code by performing, on a basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than a voltage range of a least significant bit of the first converter circuit;
• an error detector configured to detect a conversion error of the analog-to-digital conversion on a basis of the first digital code and the second digital code, and to thereby generate error data that indicates at which bit in the first digital code and what kind of conversion error has occurred;
• and
• a calibration circuit configured to estimate an error factor on a basis of the first digital code, the second digital code, and the error data, and to perform, on a basis of an estimation result on the error factor, calibration of a circuit relevant to the error factor estimated, among circuits included in the first converter circuit and the second converter circuit, wherein
• the first converter circuit includes
• two or more comparator circuits that include a first comparator circuit and a second comparator circuit and that are each configured to perform a comparison operation, and
• a digital-to-analog converter circuit,
• the digital-to-analog converter circuit is configured to generate a first voltage on a basis of a result of the comparison operation by the second comparator circuit,
• the first comparator circuit is configured to perform the comparison operation by comparing the first voltage with a threshold voltage,
• the error data indicates at which bit in the first digital code the conversion error has occurred and whether the conversion error is in a direction that makes bit data lower in value or in a direction that makes the bit data higher in value, and
• the calibration circuit is configured to calculate a degree of correlation between the first digital code and the direction of the conversion error on a basis of the first digital code and the error data, and to estimate a mismatch of a gain of the digital-to-analog converter circuit on a basis of the degree of correlation.

An analog-to-digital converter circuit comprising:

• a first converter circuit configured to generate a first digital code by performing analog-to-digital conversion on a basis of an input voltage;
• a second converter circuit configured to generate a second digital code by performing, on a basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than a voltage range of a least significant bit of the first converter circuit;
• an error detector configured to detect a conversion error of the analog-to-digital conversion on a basis of the first digital code and the second digital code, and to thereby generate error data that indicates at which bit in the first digital code and what kind of conversion error has occurred;
• and
• a calibration circuit configured to estimate an error factor on a basis of the first digital code, the second digital code, and the error data, and to perform, on a basis of an estimation result on the error factor, calibration of a circuit relevant to the error factor estimated, among circuits included in the first converter circuit and the second converter circuit, wherein
• the second converter circuit includes a fourth comparator circuit configured to perform a comparison operation, and
• the calibration circuit is configured to calculate a rate of occurrence of the conversion error on a basis of the second digital code, and to estimate a shift of a threshold voltage of the fourth comparator circuit on a basis of the rate of occurrence.

An analog-to-digital converter circuit comprising:

• a first converter circuit configured to generate a first digital code by performing analog-to-digital conversion on a basis of an input voltage;
• a second converter circuit configured to generate a second digital code by performing, on a basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than a voltage range of a least significant bit of the first converter circuit;
• an error detector configured to detect a conversion error of the analog-to-digital conversion on a basis of the first digital code and the second digital code, and to thereby generate error data that indicates at which bit in the first digital code and what kind of conversion error has occurred;
• and
• a calibration circuit configured to estimate an error factor on a basis of the first digital code, the second digital code, and the error data, and to perform, on a basis of an estimation result on the error factor, calibration of a circuit relevant to the error factor estimated, among circuits included in the first converter circuit and the second converter circuit, wherein
• the second converter circuit further includes an amplifier circuit, and a fourth comparator circuit that is configured to perform a comparison operation by comparing an output voltage of the amplifier circuit with a threshold voltage, and
• the calibration circuit is configured to calculate a rate of occurrence of the conversion error on a basis of the second digital code, and to estimate a mismatch of a gain of the amplifier circuit on a basis of the rate of occurrence.

An analog-to-digital converter circuit comprising:

• a first converter circuit configured to generate a first digital code by performing analog-to-digital conversion on a basis of an input voltage;
• a second converter circuit configured to generate a second digital code by performing, on a basis of the input voltage and the first digital code, analog-to-digital conversion over a voltage range wider than a voltage range of a least significant bit of the first converter circuit;
• an error detector configured to detect a conversion error of the analog-to-digital conversion on a basis of the first digital code and the second digital code, and to thereby generate error data that indicates at which bit in the first digital code and what kind of conversion error has occurred;
• a calibration circuit configured to estimate an error factor on a basis of the first digital code, the second digital code, and the error data, and to perform, on a basis of an estimation result on the error factor, calibration of a circuit relevant to the error factor estimated, among circuits included in the first converter circuit and the second converter circuit;
• and
• a signal generation circuit, wherein
• the analog-to-digital converter circuit has a first mode and a second mode,
• in the first mode, the signal generation circuit is configured to generate an alternating current voltage, and the first converter circuit is configured to generate the first digital code by performing analog-to-digital conversion on a basis of the alternating current voltage, and
• in the second mode, the first converter circuit is configured to generate the first digital code by performing analog-to-digital conversion on a basis of externally supplied voltage.