Cantilever nanoelectromechanical decoder circuit and methods for forming the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Feng Kao, Katherine H. Chiang, Jyun-Yan Kuo, Wei Lee
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Abstract
A device structure includes a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate; first access lines electrically connected to a respective row of memory cells within the two-dimensional array; and a first decoder circuit including first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the first access lines.
Claims20
A device structure comprising:
- a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate;
- a plurality of first access lines, wherein each of the plurality of access lines are electrically connected to a respective row of memory cells within the two-dimensional array;
- and
- a first decoder circuit comprising a plurality of first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells, wherein the plurality of first cantilever nanoelectromechanical devices are embedded in upper dielectric material layers, and have output nodes that are electrically connected to a respective first access line selected from the plurality of first access lines.
A device structure comprising:
- a two-dimensional array of memory cells embedded in a memory-level dielectric layer and overlying a substrate;
- a plurality of first access lines, wherein each of the plurality of first access lines is electrically connected to a respective row of memory cells within the two-dimensional array;
- and
- a first decoder circuit comprising a plurality of first cantilever nanoelectromechanical devices that overlie the two-dimensional array of memory cells and configured to activate a selected first access line selected from the plurality of first access lines, wherein each of the plurality of first cantilever nanoelectromechanical devices comprises:
- first gated nanoelectromechanical switches that are connected to each other in a parallel connection between a first source electrode and a common output node;
- and
- second gated nanoelectromechanical switches that are connected to each other in a series connection between a second source electrode and the common output node.
A method of forming a device structure, the method comprising:
- forming a two-dimensional array of memory cells and first access lines over a substrate, wherein the first access lines are electrically connected to a respective row of memory cells within the two-dimensional array;
- and
- forming a first decoder circuit comprising first cantilever nanoelectromechanical devices over the two-dimensional array of memory cells, wherein the first cantilever nanoelectromechanical devices have output nodes that are electrically connected to a respective first access line selected from the first access lines.
Dependencies are inferred from the claim text.