Dual vector arithmetic logic unit
AssigneeAdvanced Micro Devices, Inc.
InventorsBin He, Brian Emberling, Mark Leather, Michael Mantor
Life of this patent
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Abstract
A processing system executes wavefronts at multiple arithmetic logic unit (ALU) pipelines of a single instruction multiple data (SIMD) unit in a single execution cycle. The ALU pipelines each include a number of ALUs that execute instructions on wavefront operands that are collected from vector general process register (VGPR) banks at a cache and output results of the instructions executed on the wavefronts at a buffer. By storing wavefronts supplied by the VGPR banks at the cache, a greater number of wavefronts can be made available to the SIMD unit without increasing the VGPR bandwidth, enabling multiple ALU pipelines to execute instructions during a single execution cycle.
Claims20
A system comprising:
- a cache to store a set of operands transferred from a set of vector general purpose register (VGPR) banks;
- and
- an execution unit comprising a first arithmetic logic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction at each of the first ALU pipeline and the second ALU pipeline using the first set of operands in an execution cycle or a pair of independent instructions at respective ALU pipelines of the first ALU pipeline and the second ALU pipeline using the first set of operands in the execution cycle.
An apparatus, comprising:
- a set of vector general purpose register (VGPR) banks to store a set of vectors;
- a cache to store the set of vectors transferred from the set of VGPR banks;
- and
- an execution unit comprising a first arithmetic logic unit (ALU) pipeline and a second ALU pipeline to selectively execute either a single instruction or a dual instruction on the set of vectors in an execution cycle both at the first ALU pipeline and at the second ALU pipeline.
A method, comprising:
- transferring a set of warps from a set of vector general purpose register (VGPR) banks to an execution unit via a cache;
- and
- selectively executing, at the execution unit, either a single instruction or a dual instruction on the set of warps in an execution cycle both at a first ALU pipeline and at a second ALU pipeline.
Dependencies are inferred from the claim text.