Multiple-input floating-point processing with mantissa bit extension

A method of processing a set of ‘k’ floating-point numbers to perform addition and/or subtraction, k≥3, using a hardware logic implementation, each floating-point number comprising a mantissa (mi) and an exponent (ei), wherein the method comprises:

• receiving, by a format conversion circuit in the hardware logic implementation, the set of ‘k’ floating-point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits;
• creating, by the format conversion circuit in the hardware logic implementation, a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers (yi) having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit-length ‘b’ of the mantissa (mi), wherein the ‘n’ bits comprises a number of magnitude bits, wherein ‘n’ is b+┌log2(k)┐+┌log2(k−1)┐+x bits, where x is an integer, and x≥1 and x≤3, wherein adding the extra most-significant bits comprises adding at least ┌log2(k)┐ number of most-significant bits;
• identifying, by a maximum exponent detection circuit in the hardware logic implementation, a maximum exponent (emax) among the exponents ei;
• aligning, by an alignment circuit in the hardware logic implementation, the magnitude bits of the numbers (yi) based on the maximum exponent (emax);
• and
• processing, by a processing circuit in the hardware logic implementation, the set of ‘k’ numbers (yi) concurrently;
• wherein processing of the set of ‘k’ numbers (yi) by the processing circuit involves performing a computation that is required to perform a data processing function.