Storage system

A storage system for processing a request from a host apparatus, the storage system comprising:

• a first protocol chip configured to control a protocol used for communication with the host apparatus;
• a plurality of processors configured to control the storage system;
• a first shared memory that can be read and written by the first protocol chip and the plurality of processors;
• and
• a plurality of address translation units each of which connects a corresponding processor of the plurality of processors and the first shared memory, wherein
• the address translation units translate addresses used by the respective corresponding processors of the plurality of processors into addresses used to read from or write to the first shared memory,
• the first protocol chip writes the request from the host apparatus to the first shared memory,
• a first processor among the plurality of processors reads the request from the host apparatus written to the first shared memory by the first protocol chip from the first shared memory through a first address translation unit among the plurality of address translation units that is connected to the first processor and writes a response to the request to the first shared memory through the first address translation unit,
• the first protocol chip reads the response to the request from the host apparatus written by the first processor from the first shared memory and sends the response to the host apparatus,
• the first processor among the plurality of processors
• is configured to perform a reboot process that includes a reboot of the first address translation unit connected to the first processor, and
• while the first processor is performing the reboot process, a second processor that is different from the first processor of the plurality of processors is configured to substitute for the first processor by reading a first request addressed to the first processor from the host apparatus written by the first protocol chip from the first shared memory through a second address translation unit connected to the second processor, and writing a first response to the first request to the first shared memory through the second address translation unit.