Method of identifying vulnerable regions in an integrated circuit
AssigneeBattelle Memorial Institute
InventorsAdam Gakuto Kimura, Jeremy Bellay, Thomas Kent
Life of this patent
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Abstract
A method of designing a robust integrated circuit that is not vulnerable to optical fault injection comprises training a variational autoencoder to identify regions in a target integrated circuit that are vulnerable to optical fault injection and altering the design of the target integrated circuit by altering the design of the vulnerable regions so that the target integrated circuit is no longer vulnerable to optical fault injection, thereby forming the robust integrated circuit.
Claims19
A method of identifying a vulnerable region on a target integrated circuit, the method comprising:
- training a neural network to identify regions of an integrated circuit that are vulnerable based on a known vulnerable region of a sample integrated circuit;
- identifying a vulnerable region on a target integrated circuit, that has regions that are potentially vulnerable, with the neural network;
- and
- imaging the sample integrated circuit to create sample image data and wherein training the neural network includes providing the neural network with the sample image data.
A system for identifying a region in an integrated circuit that contains vulnerable region, the system comprising:
- a neural network configured to:
- be trained to identify regions that are vulnerable based on a region that is known to be vulnerable on a sample integrated circuit;
- and
- identify a vulnerable region on a target integrated circuit that has regions that are potentially vulnerable,
- wherein:
- the neural network is trained using sample image data obtained by imaging a sample integrated circuit.
Dependencies are inferred from the claim text.