High speed charge mode digital-to-analog converter

A high-speed digital-to-analog converter (DAC) configured to convert an m-bit digital input signal into an analog output signal, the high-speed DAC comprising:

• an input that receives the m-bit digital input signal;
• an output that provides the analog output signal;
• a plurality of digital-to-charge converters provided between the input and the output, the plurality of digital-to-charge converters comprising a first digital-to-charge converter and a second digital-to-charge converter, wherein each of the plurality of digital-to-charge converters comprise one or more capacitors, wherein the one or more capacitors are charged based on the m-bit digital input signal during a pre-evaluation period, wherein a charge stored by the one or more capacitors is evaluated during an evaluation period that follows the pre-evaluation period, wherein the plurality of digital-to-charge converters receive control signals that coordinate the evaluation period and the pre-evaluation period to convert each bit of the m-bit digital input signal into a different charge value, and wherein the analog output signal is generated based on the evaluation of the charge stored by the one or more capacitors during the evaluation period;
• a first plurality of switches that independently control a timing of the pre-evaluation period and the charging of the one or more capacitors;
• and
• a second plurality of switches that independently control a timing of the evaluation period and the evaluation of the one or more capacitors, wherein:
• the first digital-to-charge converter comprises a first plurality of capacitors that are charged according to a first bit value of the m-bit digital input signal at a first pre-evaluation period, wherein the first plurality of capacitors are subject to a first charge evaluation during a first evolution period and output a first charge value representing the first bit value;
• and
• the second digital-to-charge converter comprises a second plurality of capacitors that are charged according to a second bit vale of the m-bit digital input signal at a second pre-evaluation period that is different from the first pre-evaluation period, wherein the second plurality of capacitors are subject to a second charge evaluation during a second evaluation period and output a second charge value representing the second bit value.

A method of operating a digital-to-charge converter, the method comprising:

• receiving a digital input signal;
• charging a first plurality of capacitors during a first pre-evaluation period according to a first bit value of the digital input signal at a first pre-evaluation period, wherein the first plurality of capacitors are part of a first digital-to-charge converter, wherein the first plurality of capacitors are charged with a supply voltage via at least a first switch in a first set of switches based the digital input signal;
• charging a second plurality of capacitors during a second pre-evaluation period according to a second bit value of the digital input signal at a second pre-evaluation period, wherein the second plurality of capacitors are part of a second digital-to-charge converter, wherein the second plurality of capacitors are charged with the supply voltage via at least a first switch in a second set of switches based on the digital input signal;
• changing a state of the at least the first switch in the first set of switches thereby disconnecting the first plurality of capacitors from the supply voltage during a first evaluation period;
• enabling an evaluation of charge of the first plurality of capacitors during the first evaluation period via a second switch in the first set of switches;
• changing a state of the at least the first switch in the second set of switches thereby disconnecting the second plurality of capacitors from the supply voltage during a second evaluation period;
• enabling an evaluation of charge of the second plurality of capacitors during the second evaluation period via a second switch in the second set of switches;
• and
• generating an analog output signal from the digital-to-charge converter based on the evaluation of charge of the first plurality of capacitors during the first evaluation period as well as the second plurality of capacitors during the second evaluation period, wherein the first plurality of capacitors output a first charge value representing the first bit value during the first evaluation period, and wherein the second plurality of capacitors output a second charge value representing the second bit value during the second evaluation period.