Three-dimensional stacked programmable logic fabric and processor design architecture

A method of data transfer between a processor stacked in a three-dimensional orientation above a programmable fabric device comprising:

• receiving, via the processor, one or more sets of data from a processor pipeline via one or more interfaces;
• configuring, via the processor, a first portion of a programmable fabric of the programmable fabric device comprising a plurality of partitions coupled to one or more execution units of one or more cores of the processor to perform fine-grained acceleration operations, wherein the fine-grained acceleration operations comprise extending an instruction-set architecture of the processor to initiate a custom opcode space to interface with the programmable fabric;
• receiving, via the processor, one or more additional sets of data from the processor pipeline;
• and
• configuring, via the processor, a second portion of the programmable fabric comprising one or more system memory portions reserved for the programmable fabric to interface with the processor to perform coarse-grained acceleration operations on the one or more additional sets of data.

A system comprising:

• one or more compute chiplets;
• a programmable fabric base die, wherein the one or more compute chiplets are stacked in a three-dimensional orientation above the programmable fabric base die, and wherein the programmable fabric base die comprises one or more interfaces configured to provide connections between the programmable fabric base die and the one or more compute chiplets, wherein the programmable fabric base die is operable to:
• enable data transfer between the one or more compute chiplets that are three-dimensionally stacked above the programmable fabric base die;
• and
• receive, via the one or more compute chiplets, one or more sets of data via the one or more interfaces;
• configure, via the one or more compute chiplets, a first portion of the programmable fabric base die comprising a plurality of partitions coupled to one or more portions of the one or more compute chiplets to perform fine-grained acceleration operations, wherein the fine-grained acceleration operations comprise extending an instruction-set architecture of the one or more compute chiplets to initiate a custom opcode space to interface with the programmable fabric base die;
• receive, via the one or more compute chiplets, one or more additional sets of data via the one or more interfaces;
• and
• configure, via the one or more compute chiplets, a second portion of the programmable fabric base die comprising one or more system memory portions reserved for the programmable fabric base die to interface with the one or more compute chiplets to perform coarse-grained acceleration operations on the one or more additional sets of data.