Circuit for mitigating single-event-transients

A circuit for mitigating single-effect-transients (SETs) having a first input, a second input, a first complementary input, a second complementary input, a first output and a second output, and comprising:

• a first sub-circuit comprising:
• a first p-type transistor arrangement comprising at least one p-type transistor configured to generate the first output, and
• a first n-type transistor arrangement comprising at least one n-type transistor configured to generate the second output;
• and
• a second sub-circuit comprising:
• a connecting p-type transistor arrangement comprising at least one p-type transistor,
• a connecting n-type transistor arrangement comprising at least one n-type transistor connected in series to the connecting p-type transistor arrangement, wherein a drain terminal of the at least one p-type transistor in the connecting p-type transistor arrangement and a drain terminal of the at least one n-type transistor in the connecting n-type transistor arrangement are electrically coupled to each other, and
• a second p-type transistor arrangement comprising at least one p-type transistor and a second n-type transistor arrangement comprising at least one n-type transistor, wherein
• the first output is further electrically coupled to a drain terminal of the at least one p-type transistor in the second p-type transistor arrangement,
• the second output is further electrically coupled to a drain terminal of the at least one n-type transistor in the second n-type transistor arrangement,
• a gate terminal of the at least one p-type transistor in the connecting p-type transistor arrangement and a gate terminal of the at least one n-type transistor in the second n-type transistor arrangement are controlled by the first complementary input,
• a gate terminal of the at least one n-type transistor in the connecting n-type transistor arrangement and a gate terminal of the at least one p-type transistor in the second p-type transistor arrangement are controlled by the second complementary input,
• a source terminal of the at least one p-type transistor in the second p-type transistor arrangement is electrically coupled to VDD, and
• a source terminal of the at least one n-type transistor in the second n-type transistor arrangement is electrically coupled to VSS,
• wherein the first output and the second output are electrically coupled to each other through the second sub-circuit through the connecting p-type transistor arrangement of the second sub-circuit and the connecting n-type transistor arrangement of the second sub-circuit.