Programming techniques for polarity-based memory cells
AssigneeMicron Technology, Inc.
InventorsInnocenzo Tortorelli, Mattia Boniardi, Mattia Robustelli
Life of this patent
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Abstract
Methods, systems, and devices for programming techniques for polarity-based memory cells are described. A memory device may use a first type of write operation to program one or more memory cells to a first state and a second type of write operation to program one or more memory cells to a second state. Additionally or alternatively, a memory device may first attempt to use the first type of write operation to program one or more memory cells, and then may use the second type of write operation if the first attempt is unsuccessful.
Claims20
A memory system, comprising:
- one or more memory arrays;
- and
- processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
- receive a command to write a set of memory cells within the one or more memory arrays to a first state;
- and
- perform a write operation on the set of memory cells based at least in part on the command, wherein, to perform the write operation, the processing circuitry is configured to cause the memory system to:
- apply a first pulse having a first polarity to the set of memory cells;
- identify, based at least in part on applying the first pulse and within the set of memory cells, a subset of memory cells that are in a second state;
- and
- apply, based at least in part on the identifying the subset of memory cells, a second pulse having a second polarity to the subset of memory cells to write the subset of memory cells to the first state.
A memory system, comprising:
- one or more memory arrays;
- and
- processing circuitry coupled with the one or more memory arrays and configured to cause the memory system to:
- receive a command to write a set of memory cells within the one or more memory arrays to a first state;
- and
- perform a write operation on the set of memory cells based at least in part on the command, wherein, to perform the write operation, the processing circuitry is configured to cause the memory system to:
- apply a first pulse having a first polarity to the set of memory cells;
- and
- apply, after applying the first pulse, a second pulse having a second polarity to the set of memory cells to write the set of memory cells to the first state.
A non-transitory computer-readable medium storing code, the code comprising instructions executable by one or more processors to:
- receive, at a memory device, a command to write a set of memory cells at the memory device to a first state;
- and
- perform a write operation on the set of memory cells based at least in part on the command, wherein, to perform the write operation, the instructions are executable by the one or more processors to:
- apply a first pulse having a first polarity to the set of memory cells;
- identify, based at least in part on applying the first pulse and within the set of memory cells, a subset of memory cells that are in a second state;
- and
- apply, based at least in part on the identifying the subset of memory cells, a second pulse having a second polarity to the subset of memory cells to write the subset of memory cells to the first state.
Dependencies are inferred from the claim text.