Convertible memory device
AssigneeSK hynix Inc.
InventorsGyeong Cheol Park, Min Chul Sung
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including a plurality of memory cells; a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including: a first operational circuit configured to perform a first operation according to a first sensing control signal; and a second operational circuit configured to perform a second operation according to a second sensing control signal; and an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property.
Claims22
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including:
- a first operational circuit configured to perform a first operation according to a first sensing control signal;
- and
- a second operational circuit configured to perform a second operation according to a second sensing control signal;
- and
- an operational monitoring circuit configured to provide the first sensing control signal or the second sensing control signal by monitoring whether at least some of the memory cells have a ferroelectric property based on at least any of numbers of accesses to the respective memory cells in each of the first operation and the second operation, and a consistent value status of data stored in at least a part of the memory cells in each of the first operation and the second operation.
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including:
- a first operational circuit configured to perform a first operation according to a first sensing control signal;
- and
- a second operational circuit configured to perform a second operation according to a second sensing control signal;
- and
- an operational monitoring circuit configured to:
- generate access counting values for the respective memory cells by counting numbers of accesses to the respective memory cells based on a command and an address, and
- provide the first sensing control signal or the second sensing control signal based on the access counting values.
A memory device comprising:
- a memory cell array including a plurality of memory cells;
- a sense amplifying circuit configured to sense data of the memory cells through bit lines, the sense amplifying circuit including:
- a first operational circuit configured to perform a first operation according to a first sensing control signal;
- and
- a second operational circuit configured to perform a second operation according to a second sensing control signal;
- and
- an operational monitoring circuit configured to:
- provide the first sensing control signal by detecting deteriorations of the memory cells based on the data, and
- provide the second sensing control signal by detecting fails of memory cells based on the data.
Dependencies are inferred from the claim text.