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US 12,293,193 B2Granted
Advanced processor architecture
AssigneeUbitium GmbH
InventorMartin Vorbach
Life of this patent
Estimating the term…
Abstract
The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).
Claims21
An out-of-order microprocessor having an out-of-order-mode, the out-of-order microprocessor executing instructions out of order in the out-of-order-mode, wherein, in the out-of-order-mode, some of the instructions have at least two source register references for referencing at least two source registers from which at least two operand data are received and one target register reference for referencing at least one result data register in which result data is stored, the out-of-order microprocessor comprising for the out-of-order-mode:
- a unit adapted to fetch said instructions in a fetching order from an instruction memory;
- and
- a unit adapted to issue the fetched instructions in the fetching order to a two-dimensional array of execution units,
- the execution units being adapted to produce the result data for storing in result data registers by processing operand data received from result data registers storing previously produced result data,
- the execution units beinginterconnectedin the two-dimensional array by a network that transmits processing results previously produced by execution units and stored in the result data registers as operand data to execution unit inputs,
- each of the execution units receiving an issued instruction, waiting for the operand data required for the received instruction to arrive from the result data register storing previously produced result data, processing the operand data after arrival from the network, producing the result data according to the instruction received, and storing the produced result data in a result data register for transmitting the produced result data to the network;
- wherein
- the result data is made available to receiving execution units, and after the result data has been made available to all receiving execution units requiring the result data as operand data, the respective execution unit that made the result data available becomes available for processing a new respective instruction issued from the unit adapted to issue the fetched instructions;
- and
- the result data is determined to have been transmitted to all receiving execution units requiring the result data as operand data based on records of a register positioning table, wherein the records include identifications of registers that store results of instructions and identifications of execution units that include the registers.
7 more elements
A data processing chip comprising:
- a plurality of execution units that (I) each has a unique identifier, (II) each has at least one respective result register, and (III) are arranged in a multi-dimensional array that includes interconnections that interconnect the plurality execution units;
- an instruction fetcher, wherein the instruction fetcher is adapted to fetch said instructions in a fetching order from an instruction memory;
- an instruction issuer;
- wherein:
- the data processing chip is adapted to operate in an out-of-order processing mode in which the instruction issuer issues, selectively to available execution units of the plurality of execution units, the available execution units being a subset of the plurality of execution units that have been verified to have a status of being available, issuer instructions:
- (I) based on the fetched instructions that had been fetched from the instruction memory;
- (II) in the fetching order;
- and
- (III) one or more of which each, using a respective one or more of the unique identifiers, identifies from which one or more of the plurality of execution units output data is to be received (i) via the interconnections and (ii) as operand data for execution of the issuer instruction, the output data to be received having been previously generated by the one or more of the plurality of execution units by execution of one or more of the issuer instructions that had been issued earlier in the fetching order to the one or more of the plurality of execution units;
- each of at least some of the plurality of execution units is adapted to perform the following after receiving a respective one of the one or more of the issuer instructions having the identification:
- wait for the operand data of the respective one of the issuer instructions to be received via the interconnections from the one or more of the plurality of execution units identified by the respective one or more of the unique identifiers of the respective issuer instruction;
- process the operand data of the respective one of the issuer instructions once the operand data of the respective one of the issuer instructions has been received via the interconnections, thereby producing further output data;
- and
- store the produced further output data in the at least one respective result register of the respective one of the execution units, the further output data being transmittable from the at least one respective result register as operand data to other ones of the plurality of execution units for subsequent execution of other ones of the issuer instructions.
11 more elements
A microprocessor, the microprocessor being adapted to operate on instructions and having:
- execution units arranged in an array for processing operand data and producing result data according to instructions issued and being adapted to use registers as source registers for storing operand data and target registers for storing result data;
- a network for the interconnection of the execution units;
- units adapted to fetch said instructions on which the microprocessor operates and to issue the instructions in a fetching order respectively;
- units adapted to fetch said instructions on which the microprocessor operates and to issue the instructions in a fetching order respectively;
- and
- a register positioning table adapted to reference as references to target registers for storing result data to the execution units producing the result data;
- wherein the unit for issuing the instructions in the fetching order is adapted to:
- lookup operand sources in the register positioning table for enabling the execution units to obtain the operands via the network by setting operand input references of the instruction to be issued in view of the looked up reference sources;
- issue the instructions to an available execution unit;
- and
- enter a reference to the target register for storing the result data the execution unit receiving the instruction is to produce into the register positioning table.
8 more elements
Dependencies are inferred from the claim text.