Illegal address mask method and device for cores of DSP

An illegal address mask device for cores of a DSP, comprising:

• a signal input module, comprising a first multiplexer, a PC, a second multiplexer and a controller unit, wherein the first multiplexer receives an external input instruction and a first jump instruction from the control unit and selects a first transmission path to transmit the external input instruction and the first jump instruction to the PC to obtain a PC pointer, and the second multiplexer receives the PC pointer and a second jump instruction from the control unit and selects a second transmission path to transmit the PC pointer and the second jump instruction;
• an illegal address determination module, comprising a first comparator, a first gate, a program memory, an instruction pre-decoder, an illegal address mask register group, a second comparator and a second gate, wherein the first comparator receives an instruction transmitted by the second multiplexer of the signal input module and compares the instruction with a masked address range in the illegal address mask register group;
• when the instruction transmitted by the second multiplexer is located in the masked address range, the first comparator sends out a first illegal address decision signal to inform the first gate to block the instruction;
• when the instruction transmitted by the second multiplexer is not located in the masked address range, the first gate transmits the instruction to drive the PC pointer to perform a fetch operation on the program memory;
• the instruction pre-decoder receives and pre-decodes instructions obtained by the fetch operation to obtain an address of a memory access instruction;
• whether the address of the memory access instruction is located in the masked address range is determined by the second comparator;
• when the address of the memory access instruction is located in the masked address range, the second comparator sends out a second illegal address decision signal to control the second gate to block the memory access instruction;
• when the address of the memory access instruction is not located in the masked address range, the second gate transmits the memory access instruction;
• and
• a decoding and execution module, comprising an instruction decoder, an instruction execution unit and an external interface, wherein the instruction decoder receives the memory access instruction transmitted by the second gate of the illegal address determination module, extracts contents of the memory access instruction, transmits the contents of the memory access instruction to the instruction execution unit to perform a memory access operation, and after the memory access operation is completed, output is performed by the external interface.