Host device performing near data processing function and accelerator system including the same

An accelerator system comprising:

• a host device including a unit processor;
• a memory expansion device;
• and
• an interconnect circuit configured to connect the host device and the memory expansion device,
• wherein the host device among the plurality of memory expansion devices includes:
• a host expansion control circuit configured to receive a near data processing (NDP) request provided to the unit processor;
• and
• a local memory device configured to store data corresponding to the NDP request according to control by the host expansion control circuit, and
• wherein in response to the NDP request, the host expansion control circuit performs:
• a request processing operation to perform a memory operation corresponding to the NDP request on the local memory device, the memory operation including a read operation or a write operation, and
• a computation operation using the data corresponding to the NDP request,
• wherein the host expansion control circuit comprises:
• one or more host NDP request control circuits;
• and
• an interface circuit configured to receive the NDP request, select a host NDP request control circuit from among the one or more host NDP request control circuits according to an address of the NDP request, and provide the NDP request to the selected host NDP control circuit, and
• wherein the selected host NDP request control circuit configured to control the request processing operation and the computation operation corresponding to the NDP request,
• wherein the selected host NDP request control circuit comprises:
• a filter circuit configured to identify the NDP request;
• an NDP circuit configured to produce a request for the request processing operation and to perform the computation operation according to the NDP request identified at the filter circuit;
• and
• a memory controller configured to control the local memory device according to the request for the request processing operation produced by the NDP circuit,
• wherein the host NDP request control circuit includes a cache memory connected between the filter circuit and the memory controller,
• wherein the host expansion control circuit is further configured to receive a normal request that does not require a computation operation, and
• wherein the filter circuit is further configured to identify the normal request and to bypass the identified normal request to the memory controller via the cache memory controller.