Storage devices and methods of operating storage devices

A storage device comprising:

• a nonvolatile memory device including a memory cell array that includes a plurality of word-lines stacked on a substrate, wherein a plurality of memory cells that are provided in a plurality of channel holes extend in a vertical direction with respect to the substrate, and word-line cut regions extend in a first horizontal direction and divide the plurality of word-lines into a plurality of memory blocks;
• and
• a storage controller configured to control the nonvolatile memory device,
• wherein the storage controller includes an error correction code (ECC) engine and a memory interface,
• wherein the ECC engine includes an ECC encoder and a data selector, and the data selector, in a write operation on target memory cells in a target page coupled to a target word-line from among the plurality of word-lines, is configured to:
• select outer cell bits from a plurality of sub data units in a user data, each of the plurality of sub data units including outer cell bits and inner cell bits, the outer cell bits being selected based on an error correction mode signal and a location index of each of the target memory cells that indicates a distance of the target memory cell from the target word-line, to constitute an outer ECC sector including the outer cell bits, and to provide the outer ECC sector to the ECC encoder;
• and
• wherein the ECC encoder, in the write operation, is configured to:
• ECC encode the outer cell bits of the outer ECC sector to generate outer parity bits;
• and
• ECC encode each of the plurality of sub data units to generate parity bits associated with each of the plurality of sub data units and generate a plurality of ECC sectors, each including a respective one of the plurality of sub data units and the parity bits corresponding to the respective one of the plurality of sub data units;
• wherein the memory interface is configured to transmit the plurality of ECC sectors and the outer parity bits together in a codeword set to the nonvolatile memory device, and
• wherein the storage controller is configured to group the plurality of memory cells in the target page that are coupled to each of the plurality of word-lines into outer cells and inner cells according to a distance from a word-line cut region based on the location index of each of the plurality of memory cells.

A storage device comprising:

• a nonvolatile memory device including a memory cell array that includes a plurality of word-lines stacked on a substrate, wherein a plurality of memory cells that are provided in a plurality of channel holes extend in a vertical direction with respect to the substrate, and word-line cut regions extend in a first horizontal direction and divide the plurality of word-lines into a plurality of memory blocks;
• and
• a storage controller configured to control the nonvolatile memory device,
• wherein the storage controller includes an error correction code (ECC) engine, a data selector, and a memory interface,
• wherein the ECC engine includes an ECC encoder and, the ECC encoder, in a write operation on target memory cells in a target page coupled to a target word-line from among the plurality of word-lines, is configured to:
• ECC encode each of a plurality of sub data units in user data to generate parity bits associated with each of the plurality of sub data units, each of the plurality of sub data units including outer cell bits and inner cell bits, and
• generate a plurality of ECC sectors, each including a respective one of the plurality of sub data units and the parity bits corresponding to the respective one of the plurality of sub data units;
• wherein the data selector is configured to, in the write operation, select inner cell bits, from each of the plurality of sub data units based on an error correction mode signal and a location index of each of the target memory cells that indicates a relative distance of the target memory cell from the target word-line, to constitute an inner ECC sector including the inner cell bits, and provide the inner ECC sector to the ECC engine;
• wherein the ECC engine is configured to ECC encode the inner ECC sector to generate inner parity bits;
• and
• wherein the memory interface is configured to transmit the plurality of ECC sectors and the inner parity bits together as a codeword set to the nonvolatile memory device.