General-purpose systolic array
AssigneeGoogle Inc.
InventorsReginald Clifford Young, Trevor Gale, Sushma Honnavara-Prasad, Paolo Mantovani
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Abstract
A systolic array cell is described, the cell including two general-purpose arithmetic logic units (ALUs) and register-file. A plurality of the cells may be configured in a matrix or array, such that the output of the first ALU in a first cell is provided to a second cell to the right of the first cell, and the output of the second ALU in the first cell is provided to a third cell below the first cell. The two ALUs in each cell of the array allow for processing of a different instruction in each cycle.
Claims20
A processor cell, comprising:
- a crossbar switch;
- a first floating point logic unit (FPLU) configured to:
- receive, as input to the first FPLU, output from the crossbar switch;
- and
- provide, as output from the first FPLU, input to one or more additional processing cells;
- a second FPLU configured to:
- receive, as input to the second FPLU, output from the crossbar switch;
- and
- provide, as output from the second FPLU, input to the one or more additional processing cells;
- and
- a register file configured to:
- receive, as input to the register file, the outputs from the first FPLU and the second FPLU;
- and
- provide, as output from the register file, one or more inputs to the crossbar switch.
A computation unit, comprising:
- a plurality of processor cells having a first output of a first processor cell provided as input to a second processor cell and a second output of the first processor cell provided as input to a third processor cell, wherein each processor cell comprises:
- a crossbar switch;
- a plurality of floating point logic units (FPLUs), each FPLU configured to:
- receive, as input to the FPLU, output from the crossbar switch;
- and
- provide, as output from the FPLU, input to the second or third processor cell;
- and
- a register file configured to:
- receive, as input to the register file, the outputs from the plurality of FPLUs;
- and
- provide, as output from the register file, one or more inputs to the crossbar switch.
A computing system, comprising:
- one or more memories;
- one or more processors in communication with the one or more memories;
- a plurality of cells in communication with the one or more processors, the plurality of cells having a first output of a first cell provided as input to a second cell and a second output of the first cell provided as input to a third cell, wherein each cell comprises:
- a crossbar switch;
- a plurality of floating point logic units (FPLUs), each FPLU configured to:
- receive, as input to the FPLU, output from the crossbar switch;
- and
- provide, as output from the FPLU, input to the second or third cell;
- and a register file configured to:
- receive, as input to the register file, the outputs from the plurality of FPLUs;
- and
- provide, as output from the register file, one or more inputs to the crossbar switch.
Dependencies are inferred from the claim text.