Semiconductor system
AssigneesSamsung Electronics Co., Ltd., UIF (University Industry Foundation), Yonsei University
InventorsHyun Jun Park, Woo-Seok Choi
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Abstract
A semiconductor system including a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on a matrix E, and a receiver configured to generate the plurality of data by differentially amplifying the plurality of data input/output signals received through the plurality of channels based on a matrix D, in which all components of the matrix E and the matrix D are integers, a product matrix of the matrix D and the matrix E is a diagonal matrix, a sum of the components of each row of the matrix D is 0, and a sum of absolute values of the components of each column of the matrix D is less than or equal to a threshold value.
Claims20
A semiconductor system, comprising:
- a transmitter configured to output a plurality of data as a plurality of data input/output signals through a plurality of channels based on a matrix E;
- and
- a receiver configured to generate the plurality of data by differentially amplifying the plurality of data input/output signals received through the plurality of channels based on a matrix D, all components of the matrix E and the matrix D being integers, a product matrix of the matrix D and the matrix E being a diagonal matrix, a sum of the components of each row of the matrix D being 0, and a sum of absolute values of the components of each column of the matrix D being less than or equal to a threshold value.
A memory device, comprising:
- a memory cell array;
- and
- a transmitter configured to receive n (n is a natural number) data from the memory cell array, and emphasizes the n data with intensities according to components of a matrix E to generate n+1 data input/output signals, in which a sum of the components of the matrix E is 0.
A memory system comprising:
- a memory device configured to include a memory cell array and a transmitter encoding n data into n+1 data input/output signals and outputting the n+1 data input/output signals;
- and
- a memory controller configured to include a receiver receiving the n+1 data input/output signals and decoding n data by differentially amplifying the n+1 data input/output signals according to components of a matrix D, in which a sum of the components of the matrix D is 0.
Dependencies are inferred from the claim text.