Display panel

A display panel, comprising:

• a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit;
• an interconnected reset signal supply network configured to provide a reset signal to a plurality of pixel driving circuits;
• a plurality of light emitting elements;
• and
• an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements;
• wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area;
• the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer;
• the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer;
• and
• the plurality of first signal lines are electrically connected to the plurality of second signal lines;
• wherein the interconnected reset signal supply network comprises signal lines in a display area of the display panel.

A display panel, comprising:

• a base substrate;
• a plurality of subpixels, a respective subpixel comprising a respective light emitting element and a respective pixel driving circuit;
• a plurality of light emitting elements;
• an interconnected first voltage supply network configured to provide a first voltage signal to cathodes of the plurality of light emitting elements;
• a semiconductor material layer on the base substrate;
• a planarization layer on a side of the semiconductor material layer away from the base substrate;
• a second signal line layer on a side of the planarization layer away from the semiconductor material layer;
• wherein the interconnected first voltage supply network comprises signal lines in a display area of the display panel, the display area being at least partially surrounded by a peripheral area;
• the signal lines comprise a plurality of first signal lines in a first signal line layer and a plurality of second signal lines in a second signal line layer;
• the display panel further comprises a planarization layer between the first signal line layer and the second signal line layer;
• and
• the plurality of first signal lines are electrically connected to the plurality of second signal lines;
• wherein the display panel further comprises an interconnected reset signal supply network configured to provide a reset signal to a plurality of pixel driving circuits;
• the interconnected reset signal supply network comprises a plurality of first reset signal lines respectively along a first direction and a plurality of second reset signal lines respectively along a second direction;
• and
• the semiconductor material layer comprises the plurality of first reset signal lines, and the second signal line layer comprises the plurality of second reset signal lines.