Driver circuit for low voltage differential signaling, LVDS, line driver arrangement for LVDS and method for operating an LVDS driver circuit

A driver circuit for low voltage differential signaling, LVDS, comprising

• a phase alignment circuit comprising an input configured to receive an input signal, a first output configured to provide an internal signal as a function of the input signal, and a second output configured to provide an inverted internal signal, which is the inverted signal of the internal signal, and
• an output driver circuit coupled to the phase alignment circuit, the output driver circuit comprising a first input configured to receive the internal signal, a second input configured to receive the inverted internal signal, a first output configured to provide an output signal as a function of the internal signal and a second output configured to provide an inverted output signal which is the inverted signal of the output signal,
• wherein the phase alignment circuit is configured to provide the inverted internal signal with its phase being aligned to a phase of the internal signal, wherein the phase alignment circuit comprises
• a first inverter having an input, which is connected to the input of the phase alignment circuit, an output configured to provide an inverted input signal from the input signal, a first inverter supply terminal, which is connected to a supply voltage terminal, and a first inverter reference terminal, which is connected to a reference voltage terminal,
• a second inverter having an input, which is connected to the output of the first inverter, an output configured to provide the internal signal from the inverted input signal, a second inverter supply terminal, which is connected to the supply voltage terminal via a first switch, and a second inverter reference terminal, which is connected to the reference voltage terminal via a second switch, and
• a third inverter having an input which is connected to the input of the first inverter and an output configured to provide the inverted internal signal from the input signal, a third inverter supply terminal, which is connected to the second inverter supply terminal of the second inverter and to the supply voltage terminal via a third switch, and a third inverter reference terminal which is connected to the second inverter reference terminal of the second inverter and to the reference voltage terminal via a fourth switch.