Signal line sense amplifying circuit and integrated circuit capable of calibrating driving strength of MOS transistors
AssigneeSK hynix Inc.
InventorGi Moon Hong
Life of this patent
Estimating the term…
Abstract
An integrated circuit includes an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation. The integrated circuit also includes a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation.
Claims22
An integrated circuit comprising:
- an operation control circuit configured to control generation of a sharing signal, a pre-charge signal, a sensing signal, a latch signal, and a calibration enable signal for a calibration operation and a sense amplifying operation;
- and
- a signal line sense amplifying circuit configured to receive the sharing signal, the pre-charge signal, the sensing signal, the latch signal, and the calibration enable signal to perform the calibration operation and the sense amplifying operation,
- wherein the signal line sense amplifying circuit includes metal-oxide semiconductor field-effect (MOS) transistors for driving input nodes to which input data and inverted input data are input, is configured to calibrate a driving strength of each of the MOS transistors in the calibration operation, and is configured to generate output data by sensing and amplifying the input data and the inverted input data in the sense amplifying operation performed in a state in which the calibration operation is performed.
A signal line sense amplifying circuit comprising:
- a sense amplifying circuit including metal-oxide semiconductor field-effect (MOS) transistors for driving input nodes to which input data and inverted input data are input in a calibration operation and a sense amplifying operation;
- and
- a calibration circuit configured to generate calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation,
- wherein the sense amplifying circuit is configured to sense and amplify the input data and the inverted input data to generate output data and inverted output data in the sense amplifying operation performed in a state in which the calibration operation is performed based on the calibration signals.
A signal line sense amplifying circuit comprising:
- a sense amplifying circuit including metal-oxide semiconductor field-effect (MOS) transistors for driving input nodes to which input data and inverted input data are input in a calibration operation and a sense amplifying operation;
- a first calibration circuit configured to generate first calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation;
- and
- a second calibration circuit configured to generate second calibration signals for calibrating a driving strength of each of the MOS transistors in the calibration operation,
- wherein the sense amplifying circuit is configured to sense and amplify the input data and the inverted input data to generate output data and inverted output data in the sense amplifying operation performed in a state in which the calibration operation is performed based on the first calibration signals and the second calibration signals.
Dependencies are inferred from the claim text.