Symbiotic network on layers
AssigneeAdeia Semiconductor Technologies LLC
InventorsJavier A. DeLaCruz, Belgacem Haba, Rajesh Katkar
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Abstract
The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.
Claims18
A network to horizontally and vertically route electrical communications between components of stacked device layers of a 3D system on chip (SoC), the network comprising:
- a first network layer disposed between a first device layer and a second device layer, the first device layer comprising one or more first components and the second device layer comprising one or more second components;
- a third device layer directly bonded to the second device layer, the third device layer comprising one or more third components in direct electrical communication with the one or more second components;
- and
- a second network layer disposed between the third device layer and a fourth device layer comprising one or more fourth components, wherein the first network layer and the second network layer route electrical communications between at least one of the first components and one or more of the fourth components.
Dependencies are inferred from the claim text.