Configurable MAC pipelines for finite-impulse-response filtering, and methods of operating same

An integrated circuit comprising:

• a plurality MAC pipelines wherein each MAC pipeline includes:
• (i) a plurality of multiplier-accumulator circuits connected in series to perform a plurality of concatenated multiply and accumulate operations and (ii) a plurality of data paths including an accumulation data path, and wherein each multiplier-accumulator circuit of the plurality of multiplier-accumulator circuits of each MAC pipeline includes:
• a multiplier to multiply first data by multiplier weight data and generate product data, and
• an accumulator, coupled to the multiplier of the associated multiplier-accumulator circuit, to add second data and the product data of the associated multiplier to generate sum data;
• a plurality of control/configure circuits, wherein each control/configure circuit connects directly to and is associated with one of the MAC pipelines, wherein each control/configure circuit includes a plurality of configurable data paths including:
• an accumulation data path which is configurable to directly connect to an input and an output of the accumulation data path of the associated MAC pipeline to form an accumulation ring when the associated control/configure circuit is configured in an accumulation mode, and
• an output data path which is configurable to directly connect to the output of the accumulation data path of the associated MAC pipeline to receive final accumulation data from the associated MAC pipeline when the associated control/configure circuit is configured in an output data mode.