Coarse floating point accumulator circuit, and MAC processing pipelines including same

An integrated circuit comprising:

• a multiplier-accumulator circuit execution pipeline including a plurality of multiply-accumulate (MAC) circuits to perform multiply and accumulate operations, wherein each MAC circuit includes:
• a multiplier circuit, coupled to a first memory, to multiply first input data, having a first data format, and filter weight data to generate first product data in a floating point data format, the floating point data format including an explicit sign bit, an exponent field, and a fractional field in which each constituent bit has a respective significance less than one, and
• an accumulator circuit coupled to receive the first product data from the multiplier circuit and having:
• format conversion circuitry to generates format-converted product data by converting the first product data from the floating point data format to a second data format having (i) an exponent field with fewer constituent bits than the exponent field of the floating point data format, (ii) a two's-complement numeric field having one or more bits with respective significances greater than one, and (iii) a smaller numeric range than the floating point data format, and
• addition circuitry to generate an accumulated sum by adding second input data to the format-converted product data;
• control circuitry, coupled to the accumulator circuit of each MAC circuit of the multiplier-accumulator circuit execution pipeline, to program a numeric precision of the accumulator circuit;
• wherein, the plurality of MAC circuits of the multiplier-accumulator circuit execution pipeline each perform a plurality of multiply operations and accumulate operations to process the first input data and generate processed data therefrom.

An integrated circuit comprising:

• a multiplier-accumulator circuit execution pipeline including a plurality of multiply-accumulate (MAC) circuits to perform multiply and accumulate operations, wherein each MAC circuit includes:
• a multiplier circuit, coupled to a first memory, to multiply first input data, having a first data format, and filter weight data to generate and output first product data in a floating point data format, the floating point data format having three constituent bit fields, including a sign bit, an exponent field, and a fractional field in which each constituent bit has a respective significance less than one, and
• an accumulator circuit coupled to receive the first product data from the multiplier circuit and having:
• format conversion circuitry to generate format-converted product data by converting the first product data from the floating point data format to a second data format having two constituent bit fields, including (i) an exponent field with fewer constituent bits than the exponent field of the floating point data format, (ii) a two's-complement numeric field having one or more bits with respective significances greater than one, and (iii) a smaller numeric range than the floating point data format, and
• adder circuitry to generate an accumulated sum by adding second input data to the format-converted product data.