Gate contact structure over active gate and method to fabricate same

A computing device, comprising:

• a board;
• and
• a component coupled to the board, the component including an integrated circuit structure, comprising:
• a fin comprising silicon;
• a gate structure over the fin, the gate structure comprising a gate electrode;
• a trench contact structure over the fin, wherein the trench contact structure comprises a trench cap dielectric layer directly on a top of a trench contact, the trench cap dielectric layer having a top surface above a bottom surface, and the trench cap dielectric layer having side surface between the top surface and the bottom surface;
• a gate contact via directly on a portion of the gate electrode vertically over the fin, wherein the gate contact via is further directly on and in contact with the top surface of the trench cap dielectric layer of the trench contact structure, and wherein the gate contact via is continuous from a location vertically over the gate electrode to a location vertically over the trench contact;
• and
• a dielectric spacer between the gate structure and the trench contact structure, wherein the dielectric spacer has a top at a same horizontal level as the top surface of the trench cap dielectric layer of the trench contact structure.

An integrated circuit structure, comprising:

• a fin comprising silicon;
• a gate structure over the fin, the gate structure comprising a gate electrode;
• a trench contact structure over the fin, wherein the trench contact structure comprises a trench cap dielectric layer directly on a top of a trench contact, the trench cap dielectric layer having a top surface above a bottom surface, and the trench cap dielectric layer having a side surface between the top surface and the bottom surface;
• a gate contact via directly on a portion of the gate electrode vertically over the fin, wherein the gate contact via is further directly on and in contact with the top surface of the trench cap dielectric layer of the trench contact structure, wherein the gate structure comprises a gate cap dielectric layer on the gate electrode, wherein the gate contact via is in an opening of the gate cap dielectric layer, and wherein the gate cap dielectric layer of the gate structure has an uppermost surface co-planar with an uppermost surface of the trench cap dielectric layer;
• and
• a dielectric spacer between the gate structure and the trench contact structure, wherein the dielectric spacer has a top at a same horizontal level as the top surface of the trench cap dielectric layer of the trench contact structure.

An integrated circuit structure, comprising:

• a fin comprising silicon;
• a gate structure over the fin, the gate structure comprising a gate electrode;
• a trench contact structure over the fin, wherein the trench contact structure comprises a trench cap dielectric layer directly on a top of a trench contact, the trench cap dielectric layer having a top surface above a bottom surface, and the trench cap dielectric layer having a side surface between the top surface and the bottom surface;
• a gate contact via directly on a portion of the gate electrode vertically over the fin, wherein the gate contact via is further directly on and in contact with the top surface of the trench cap dielectric layer of the trench contact structure, and wherein the gate contact via is continuous from a location vertically over the gate electrode to a location vertically over the trench contact;
• and
• a second trench contact structure over the fin, wherein the second trench contact structure comprises a second trench cap dielectric layer on a top of a second trench contact, and wherein the gate contact via is further directly on a portion of the second trench cap dielectric layer of the second trench contact structure.