Memory structure and method for operating the same

A method for operating a memory structure, comprising:

• a forward propagation step comprising:
• inputting a plurality of input signals to a plurality of memory cells in a memory structure through a plurality of bit lines;
• producing a plurality of cell currents by the plurality of memory cells to a plurality of source lines on the basis of a plurality of weights stored in the plurality of memory cells;
• calculating sums of the plurality of cell currents on each source line to produce a plurality of source line currents;
• and
• converting the plurality of source line currents to an output signal;
• and
• a backward propagation step comprising:
• inputting a plurality of error input signals to the plurality of memory cells in the memory structure through a plurality of word lines;
• producing a plurality of error cell currents by the plurality of memory cells to the plurality of bit lines on the basis of the plurality of error input signals;
• calculating sums of the plurality of error cell currents on each bit line to obtain a plurality of error bit line currents;
• converting the plurality of error bit line currents to an error output signal;
• and
• updating the plurality of weights in the plurality of memory cells on the basis of the error output signal.

A method for operating a memory structure, comprising:

• a forward propagation step comprising:
• inputting a plurality of first input signals to a first memory cell array in a memory structure through a plurality of first bit lines;
• producing a plurality of first cell currents by the first memory cell array to a plurality of first source lines on the basis of a plurality of first weights stored in the first memory cell array;
• calculating sums of the plurality of first cell currents on each first source line to produce a plurality of first source line currents;
• inputting a plurality of second input signals to a second memory cell array in the memory structure through a plurality of second bit lines;
• producing a plurality of second cell currents by the second memory cell array to a plurality of second source lines on the basis of a plurality of second weights stored in the second memory cell array;
• calculating sums of the plurality of second cell currents on each second source line to obtain a plurality of second source line currents;
• and
• converting the plurality of first source line currents and the plurality of second source line currents to an output signal,
• wherein the plurality of first weights are positive weights, and the plurality of second weights are negative weights.