Memory device interface and method

A memory apparatus, comprising:

• a substrate,
• a host physical interface to memory, the host physical interface including connections for at least one memory channel, the connections for the memory channel including command/address (CA) connections, data connections (DQs), and ECC data/parity connections (ECC DQs), wherein the memory channel includes at least 32 DQs and at least 4 ECC DQs;
• and
• multiple DRAM devices supported by the substrate, the multiple memory devices connected to form at least nine sub-channels, each sub-channel including respective portions of at least two DRAM devices, wherein memory cells of the respective DRAM portions are accessible by local word lines which extend only within the respective DRAM portion, and which are driven by respective sub-word line drivers;
• wherein memory cells of each sub-channel are independently addressable from memory cells of other sub-channels, and wherein each sub-channel includes at least two data paths, each data path associated with a respective data DQ or ECC DQ;
• wherein a bit width of each sub-channel, and independent operability of each DRAM portion, are configured to facilitate, via the host physical interface, at least one of error detection and error correction, of data in at least a single data path within a sub-channel;
• and
• wherein each DRAM portion in a sub-channel includes a first number of array mats along a first direction in which a global word line extends, and a second number of array mats along a second direction perpendicular to the first direction, wherein the second number of array mats in the second direction is greater than the first number of array mats along the first direction.

A memory module, comprising:

• a substrate having a host physical interface, the host physical interface including connections for multiple memory channels, the connections for each memory channel including respective command/address (CA) connections, data connections (DQs), and ECC data/parity connections (ECC DQs);
• multiple DRAM devices connected to form multiple sub-channels, each sub-channel including a respective DRAM portion in at least one DRAM device, wherein each sub-channel receives data from a subset of the data DQs and ECC DQs, wherein local word lines in each DRAM portion are independently addressable relative to local word lines in other DRAM portions;
• wherein each DRAM portion in a sub-channel comprises:
• a first number of array mats along a first direction in which a global word line extends, and a second number of array mats along a second direction perpendicular to the first direction;
• wherein the second number of array mats in the second direction is greater than the first number of array mats along the first direction;
• wherein each array mat has respective sub-word line drivers independently addressable from other array mats within the multiple sub-channels;
• wherein the multiple memory channels are DDR5-compatible memory channels, which includes 32 DQs and more than 4 ECC DQs;
• and wherein the multiple DRAM devices are connected to form at least 18 sub-channels, and wherein each DRAM portion of the respective sub-channels is associated with at least 2 DQs or 2 ECC DQs of the memory channel;
• and
• wherein recovery from a failed DRAM portion in a sub-channel can be performed under control of a host through the host interface, through use of the ECC DQs.