Link-quality estimation and anomaly detection in high-speed wireline receivers
AssigneeMarvell Asia Pte Ltd
InventorsVenugopal Balasubramonian, Lenin Kumar Patra
Life of this patent
Estimating the term…
Abstract
An integrated Circuit (IC) for use in a network device includes a receiver and a Link Quality Estimation Circuit (LQEC). The receiver is configured to receive a signal over a link and to process the received signal. The LQEC is configured to predict a link quality measure indicative of communication quality over the link in the future, by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.
Claims16
An Integrated Circuit (IC) for use in a network device, the IC comprising:
- a receiver, which is configured to receive a signal over a link and to process the received signal;
- and
- a Link Quality Estimation Circuit (LQEC), which is configured to run an Artificial Prediction (AI) model that predicts a link quality measure indicative of a probability that the link will fail within a future time interval having a predefined length, wherein the AI model predicts the link quality measure by analyzing at least one or more settings of circuitry of the receiver, and to initiate a responsive action depending on the predicted link quality measure.
A method for use in a network device, the method comprising:
- using a receiver, receiving a signal over a link and processing the received signal;
- running an Artificial Prediction (AI) model that predicts a link quality measure indicative of a probability that the link will fail within a future time interval having a predefined length, wherein the AI model predicts the link quality measure by analyzing at least one or more settings of circuitry of the receiver;
- and
- initiating a responsive action depending on the predicted link quality measure.
Dependencies are inferred from the claim text.